[llvm] [AArch64] Add lowering for `@llvm.experimental.vector.compress` (PR #101015)

[David Green via llvm-commits]

davemgreen wrote:

> I tried to implement this in GlobalISel too, but there seem to be some issues with SVE there and non-legal types. So I cannot implement the same behavior in both SelectionDAG and GlobalISel. Does it make sense to skip GlobalISel for now or implement a part of the feature and then add stuff later? This can also be in a separate PR.

Yeah - There isn't a lot of GISel SVE support at the moment, just the very basics.

> @davemgreen I'm working on this right now. For i8/i16 vectors with 2 or 4 elements, this is trivial, as we can just extend the "container" vector. For vectors with more elements, e.g., <vscale x 16 x i8> I'm trying to convert this to <vscale x 16 x i32> and then let DAGTypeLegalizer::SplitVecRes_VECTOR_COMPRESS handle the illegal type again. But I'm stuck here a bit. After returning a VECTOR_COMPRESS with a 16 x i32 vector from the custom lowering, the next step tries to expand this, which fails for scalable vectors.

> Is there a way to "ignore" this for now and let it get legalized first, which contains the logic for recursively splitting and merging large vectors with VECTOR_COMPRESS?

Sorry for not replying earlier - my understanding is that we are going from "no support" to "some support", so something working is better than nothing!

https://github.com/llvm/llvm-project/pull/101015