[llvm] [SelectionDAG] Scalarize binary ops of splats before legal types (PR #100749)

[Luke Lau via llvm-commits]

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@@ -864,21 +864,19 @@ define <vscale x 8 x i64> @vmul_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
 }
 
 define <vscale x 8 x i64> @vmul_xx_nxv8i64(i64 %a, i64 %b) nounwind {
-; RV32-LABEL: vmul_xx_nxv8i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
-; RV32-NEXT:    vlse64.v v8, (a0), zero
-; RV32-NEXT:    sw a3, 4(sp)
-; RV32-NEXT:    sw a2, 0(sp)
-; RV32-NEXT:    mv a0, sp
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vmul.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; RV32NOM-LABEL: vmul_xx_nxv8i64:
+; RV32NOM:       # %bb.0:
+; RV32NOM-NEXT:    addi sp, sp, -16
+; RV32NOM-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32NOM-NEXT:    call __muldi3
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lukel97 wrote:

I think +v without +m is a very unusual configuration, so I'm not too concerned about this case

https://github.com/llvm/llvm-project/pull/100749