[llvm] [Mips] Add test for AND optimization (PR #102278)

[via llvm-commits]

https://github.com/yingopq created https://github.com/llvm/llvm-project/pull/102278

for issue #42826

>From 8f1d59febcac4e3335a00b2d6a8b423a7449a2ef Mon Sep 17 00:00:00 2001
From: Ying Huang <ying.huang at oss.cipunited.com>
Date: Wed, 7 Aug 2024 03:01:28 -0400
Subject: [PATCH] [Mips] Add test for AND optimization

for issue #42826
---
 llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll | 28 +++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll

diff --git a/llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll b/llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll
new file mode 100644
index 00000000000000..988a0f5ee5ba3a
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64 | FileCheck %s \
+; RUN:    -check-prefix=MIPS4
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r2 | FileCheck %s \
+; RUN:    -check-prefix=MIPS64R2
+
+define i64 @foo(i64 noundef %a) {
+; MIPS4-LABEL: foo:
+; MIPS4:       # %bb.0: # %entry
+; MIPS4-NEXT:   sll    $1, $4, 0
+; MIPS4-NEXT:   srl    $1, $1, 2
+; MIPS4-NEXT:   andi   $1, $1, 7
+; MIPS4-NEXT:   daddiu $2, $zero, 1
+; MIPS4-NEXT:   jr     $ra
+; MIPS4-NEXT:   dsllv  $2, $2, $1
+;
+; MIPS64R2-LABEL: foo:
+; MIPS64R2:       # %bb.0: # %entry
+; MIPS64R2-NEXT:   sll	  $1, $4, 0
+; MIPS64R2-NEXT:   ext	  $1, $1, 2, 3
+; MIPS64R2-NEXT:   daddiu $2, $zero, 1
+; MIPS64R2-NEXT:   jr     $ra
+; MIPS64R2-NEXT:   dsllv  $2, $2, $1
+entry:
+  %div1 = lshr i64 %a, 2
+  %and = and i64 %div1, 7
+  %shl = shl nuw nsw i64 1, %and
+  ret i64 %shl
+}