[llvm] [MIPS] Fix missing ANDI optimization (PR #97689)

[via llvm-commits]

https://github.com/yingopq updated https://github.com/llvm/llvm-project/pull/97689

>From 486cd36efea8ecf93eadc47a52884b74e98183e2 Mon Sep 17 00:00:00 2001
From: Ying Huang <ying.huang at oss.cipunited.com>
Date: Thu, 4 Jul 2024 04:05:57 -0400
Subject: [PATCH] [MIPS] Fix missing ANDI optimization

1. Add MipsPat to optimize (andi (srl (truncate i64 $1), x), y) to
   (andi (truncate (dsrl i64 $1, x)), y).
2. Add MipsPat to optimize (ext (truncate i64 $1), x, y) to
   (truncate (dext i64 $1, x, y)).

The assembly result is the same as gcc.

Fix #42826
---
 llvm/lib/Target/Mips/Mips64InstrInfo.td   |  6 ++++++
 llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll | 26 +++++++++++++++++++++++
 2 files changed, 32 insertions(+)
 create mode 100644 llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll

diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index f6ac3091a3ba8..cb9a0d44a7a72 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -830,6 +830,12 @@ def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
               ISA_MIPS3, GPR_64;
+def : MipsPat<(and (srl (i32 (trunc GPR64:$src)), immZExt5:$imm5), immZExt16:$value),
+              (ANDi (EXTRACT_SUBREG (DSRL GPR64:$src, immZExt5:$imm5), sub_32), immZExt16:$value)>,
+              ISA_MIPS3, GPR_64;
+def : MipsPat<(MipsExt (i32 (trunc GPR64:$src)), immZExt5:$pos, immZExt5:$size),
+              (EXTRACT_SUBREG (DEXT GPR64:$src, immZExt5:$pos, immZExt5:$size), sub_32)>,
+              ISA_MIPS3, GPR_64;
 
 // 32-to-64-bit extension
 def : MipsPat<(i64 (anyext GPR32:$src)),
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll b/llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll
new file mode 100644
index 0000000000000..d154f13c8b59d
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/llvm-ir/and-srl.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64 | FileCheck %s \
+; RUN:    -check-prefix=MIPS4
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r2 | FileCheck %s \
+; RUN:    -check-prefix=MIPS64R2
+
+define i64 @foo(i64 noundef %a) {
+; MIPS4-LABEL: foo:
+; MIPS4:       # %bb.0: # %entry
+; MIPS4-NEXT:   dsrl   $1, $4, 2
+; MIPS4-NEXT:   andi   $1, $1, 7
+; MIPS4-NEXT:   daddiu $2, $zero, 1
+; MIPS4-NEXT:   jr     $ra
+; MIPS4-NEXT:   dsllv  $2, $2, $1
+;
+; MIPS64R2-LABEL: foo:
+; MIPS64R2:       # %bb.0: # %entry
+; MIPS64R2-NEXT:   dext	  $1, $4, 2, 3
+; MIPS64R2-NEXT:   daddiu $2, $zero, 1
+; MIPS64R2-NEXT:   jr     $ra
+; MIPS64R2-NEXT:   dsllv  $2, $2, $1
+entry:
+  %div1 = lshr i64 %a, 2
+  %and = and i64 %div1, 7
+  %shl = shl nuw nsw i64 1, %and
+  ret i64 %shl
+}