[llvm] [AArch64] Don't replace dst of SWP instructions with (X|W)ZR (PR #102139)

[Luke Geeson via llvm-commits]

lukeg101 wrote:

thanks for fixing this @pratlucas !

the patch looks good to me, I note that this semantics applies to CAS/SWP/LD<op> and ST<OP> variants, so if CAS is used as the target of an atomic in the future in a similar fashion, the behaviour will arise again. Currently CAS is used in other op that requires the dst, and so it’s fine for now.

> Should this be backported to 19.x?

Yes I think so, it’s relatively harmless a fix but ensures translation of atomic RMW intrinsics, it shouldn’t affect other backends 

https://github.com/llvm/llvm-project/pull/102139