[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)

[Pengcheng Wang via llvm-commits]

================
@@ -45,6 +154,13 @@ defvar SiFiveP400FloatArith  = SiFiveP400FEXQ0;
 defvar SiFiveP400F2I      = SiFiveP400FEXQ0;
 def SiFiveP400FloatDiv    : ProcResource<1>;
 
+// Vector pipeline
+def SiFiveP400VEXQ0        : ProcResource<1>;
----------------
wangpc-pp wrote:

`EXQ0` means `execution queue 0`? But it seems there is no second unit and all arithmetic operations are executed on this unit (not a quene?).

https://github.com/llvm/llvm-project/pull/102155