[llvm] b64ec3c - [SLP] The order of store chains needs to consider the size of the values. (#101810)

[via llvm-commits]

Author: tcwzxx
Date: 2024-08-07T11:01:53+08:00
New Revision: b64ec3c9faf0adce6e92c69fb48a7c7473c57200

URL: https://github.com/llvm/llvm-project/commit/b64ec3c9faf0adce6e92c69fb48a7c7473c57200
DIFF: https://github.com/llvm/llvm-project/commit/b64ec3c9faf0adce6e92c69fb48a7c7473c57200.diff

LOG: [SLP] The order of store chains needs to consider the size of the values. (#101810)

When store chains have the same value type ID and pointer type ID, they
may mix different sizes of values, such as i8 and i64. This can lead to
missed vectorization opportunities.

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    llvm/test/Transforms/SLPVectorizer/X86/stores_mix_sizes.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index f1e64bf5dbae2..c9335b7a89e12 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -19159,6 +19159,12 @@ bool SLPVectorizerPass::vectorizeStoreChains(BoUpSLP &R) {
     if (V->getPointerOperandType()->getTypeID() >
         V2->getPointerOperandType()->getTypeID())
       return false;
+    if (V->getValueOperand()->getType()->getScalarSizeInBits() <
+        V2->getValueOperand()->getType()->getScalarSizeInBits())
+      return true;
+    if (V->getValueOperand()->getType()->getScalarSizeInBits() >
+        V2->getValueOperand()->getType()->getScalarSizeInBits())
+      return false;
     // UndefValues are compatible with all other values.
     if (isa<UndefValue>(V->getValueOperand()) ||
         isa<UndefValue>(V2->getValueOperand()))

diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/stores_mix_sizes.ll b/llvm/test/Transforms/SLPVectorizer/X86/stores_mix_sizes.ll
index 1e2a87b12807c..3795b0e7b399b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/stores_mix_sizes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/stores_mix_sizes.ll
@@ -5,17 +5,9 @@ define void @test(ptr %p) {
 ; CHECK-SAME: ptr [[P:%.*]]) {
 ; CHECK-NEXT:  [[ENTRY:.*:]]
 ; CHECK-NEXT:    [[IDX1:%.*]] = getelementptr i8, ptr [[P]], i64 1
-; CHECK-NEXT:    store i8 0, ptr [[IDX1]], align 4
 ; CHECK-NEXT:    [[IDX_64_9:%.*]] = getelementptr i64, ptr [[P]], i64 9
 ; CHECK-NEXT:    store i64 1, ptr [[IDX_64_9]], align 8
-; CHECK-NEXT:    [[IDX2:%.*]] = getelementptr i8, ptr [[P]], i64 2
-; CHECK-NEXT:    store <4 x i8> zeroinitializer, ptr [[IDX2]], align 4
-; CHECK-NEXT:    [[IDX6:%.*]] = getelementptr i8, ptr [[P]], i64 6
-; CHECK-NEXT:    store i8 0, ptr [[IDX6]], align 4
-; CHECK-NEXT:    [[IDX7:%.*]] = getelementptr i8, ptr [[P]], i64 7
-; CHECK-NEXT:    store i8 0, ptr [[IDX7]], align 4
-; CHECK-NEXT:    [[IDX8:%.*]] = getelementptr i8, ptr [[P]], i64 8
-; CHECK-NEXT:    store i8 0, ptr [[IDX8]], align 4
+; CHECK-NEXT:    store <8 x i8> zeroinitializer, ptr [[IDX1]], align 4
 ; CHECK-NEXT:    ret void
 ;
   entry: