[llvm] [Attributor] Fix an issue that an access is skipped by mistake (PR #101862)

[Shilei Tian via llvm-commits]

https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/101862

>From fdc014a2c7240cd0d067c3503001c8ddce41940e Mon Sep 17 00:00:00 2001
From: Mark de Wever <koraq at xs4all.nl>
Date: Sun, 4 Aug 2024 15:49:54 +0200
Subject: [PATCH] [NFC][libc++][exceptions] Adds tests for LWG3112. (#100881)

The tests kept being based on std::string instead of std::string_view to
allow testing with older C++ dialects.

Adds tests for:
- LWG3112 system_error and filesystem_error constructors taking a string
may not be able to meet their postconditions
---
 .../Transforms/IPO/AttributorAttributes.cpp   | 28 +++----
 .../indirect-call-set-from-other-function.ll  | 73 +++++++++++++++++++
 2 files changed, 87 insertions(+), 14 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll

diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
index 77026c6aa5b27..db5e94806e9a1 100644
--- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
@@ -1325,20 +1325,20 @@ struct AAPointerInfoImpl
 
         const auto *FnReachabilityAA = A.getAAFor<AAInterFnReachability>(
             QueryingAA, IRPosition::function(Scope), DepClassTy::OPTIONAL);
-
-        // Without going backwards in the call tree, can we reach the access
-        // from the least dominating write. Do not allow to pass the instruction
-        // itself either.
-        bool Inserted = ExclusionSet.insert(&I).second;
-
-        if (!FnReachabilityAA ||
-            !FnReachabilityAA->instructionCanReach(
-                A, *LeastDominatingWriteInst,
-                *Acc.getRemoteInst()->getFunction(), &ExclusionSet))
-          WriteChecked = true;
-
-        if (Inserted)
-          ExclusionSet.erase(&I);
+        if (FnReachabilityAA) {
+          // Without going backwards in the call tree, can we reach the access
+          // from the least dominating write. Do not allow to pass the
+          // instruction itself either.
+          bool Inserted = ExclusionSet.insert(&I).second;
+
+          if (!FnReachabilityAA->instructionCanReach(
+                  A, *LeastDominatingWriteInst,
+                  *Acc.getRemoteInst()->getFunction(), &ExclusionSet))
+            WriteChecked = true;
+
+          if (Inserted)
+            ExclusionSet.erase(&I);
+        }
       }
 
       if (ReadChecked && WriteChecked)
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll b/llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll
new file mode 100644
index 0000000000000..f419d89a7f0a4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll
@@ -0,0 +1,73 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s -o - | FileCheck %s
+
+ at g_fn = addrspace(1) global ptr null
+
+;.
+; CHECK: @g_fn = addrspace(1) global ptr null
+;.
+define void @set_fn(ptr %fn) {
+; CHECK-LABEL: define {{[^@]+}}@set_fn
+; CHECK-SAME: (ptr [[FN:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    store ptr [[FN]], ptr addrspace(1) @g_fn, align 8
+; CHECK-NEXT:    ret void
+;
+entry:
+  store ptr %fn, ptr addrspace(1) @g_fn
+  ret void
+}
+
+define void @get_fn(ptr %fn) {
+; CHECK-LABEL: define {{[^@]+}}@get_fn
+; CHECK-SAME: (ptr [[FN:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOAD:%.*]] = load ptr, ptr addrspace(1) @g_fn, align 8
+; CHECK-NEXT:    store ptr [[LOAD]], ptr [[FN]], align 8
+; CHECK-NEXT:    ret void
+;
+entry:
+  %load = load ptr, ptr addrspace(1) @g_fn
+  store ptr %load, ptr %fn
+  ret void
+}
+
+define void @foo() {
+; CHECK-LABEL: define {{[^@]+}}@foo
+; CHECK-SAME: () #[[ATTR1:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[FN:%.*]] = alloca ptr, align 8, addrspace(5)
+; CHECK-NEXT:    store ptr null, ptr addrspace(5) [[FN]], align 8
+; CHECK-NEXT:    [[FN_CAST:%.*]] = addrspacecast ptr addrspace(5) [[FN]] to ptr
+; CHECK-NEXT:    call void @get_fn(ptr [[FN_CAST]])
+; CHECK-NEXT:    [[LOAD:%.*]] = load ptr, ptr addrspace(5) [[FN]], align 8
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp ne ptr [[LOAD]], null
+; CHECK-NEXT:    br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[LOAD_1:%.*]] = load ptr, ptr addrspace(5) [[FN]], align 8
+; CHECK-NEXT:    call void [[LOAD_1]]()
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %fn = alloca ptr, addrspace(5)
+  store ptr null, ptr addrspace(5) %fn
+  %fn.cast = addrspacecast ptr addrspace(5) %fn to ptr
+  call void @get_fn(ptr %fn.cast)
+  %load = load ptr, ptr addrspace(5) %fn
+  %tobool = icmp ne ptr %load, null
+  br i1 %tobool, label %if.then, label %if.end
+
+if.then:
+  %load.1 = load ptr, ptr addrspace(5) %fn
+  call void %load.1()
+  br label %if.end
+
+if.end:
+  ret void
+}
+;.
+; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
+; CHECK: attributes #[[ATTR1]] = { "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
+;.