[llvm] [SPIR-V] Rework usage of virtual registers' types and classes (PR #101732)

[Farzon Lotfi via llvm-commits]

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@@ -308,93 +308,104 @@ static void widenScalarLLTNextPow2(Register Reg, MachineRegisterInfo &MRI) {
     MRI.setType(Reg, LLT::scalar(NewSz));
 }
 
+inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
+  bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
+  return IsFloat ? true
+                 : SpvType->getOpcode() == SPIRV::OpTypeVector &&
+                       GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())
+                               ->getOpcode() == SPIRV::OpTypeFloat;
+}
+
+static const TargetRegisterClass *getRegClass(SPIRVType *SpvType,
+                                              const SPIRVGlobalRegistry &GR) {
+  unsigned Opcode = SpvType->getOpcode();
+  switch (Opcode) {
+  case SPIRV::OpTypeFloat:
+    return &SPIRV::fIDRegClass;
+  case SPIRV::OpTypePointer:
+    return GR.getPointerSize() == 64 ? &SPIRV::pID64RegClass
+                                     : &SPIRV::pID32RegClass;
+  case SPIRV::OpTypeVector: {
+    SPIRVType *ElemType =
+        GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
+    unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;
+    if (ElemOpcode == SPIRV::OpTypeFloat)
+      return &SPIRV::vfIDRegClass;
+    if (ElemOpcode == SPIRV::OpTypePointer)
+      return GR.getPointerSize() == 64 ? &SPIRV::vpID64RegClass
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farzonl wrote:

do  these 32 and 64 bit register classes have any effect on all the hard coded `LLT LLTy = LLT::scalar(32);` throughout the code base?

https://github.com/llvm/llvm-project/pull/101732