[llvm] [RISCV] Support llvm.masked.expandload intrinsic (PR #101954)

[Craig Topper via llvm-commits]

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@@ -10760,16 +10762,50 @@ SDValue RISCVTargetLowering::lowerMaskedLoad(SDValue Op,
   if (!VL)
     VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
 
-  unsigned IntID =
-      IsUnmasked ? Intrinsic::riscv_vle : Intrinsic::riscv_vle_mask;
+  SDValue Index;
+  if (!IsUnmasked && IsExpandingLoad) {
+    MVT IndexVT = ContainerVT;
+    if (ContainerVT.isFloatingPoint())
+      IndexVT = IndexVT.changeVectorElementTypeToInteger();
+
+    MVT IndexEltVT = IndexVT.getVectorElementType();
+    if (Subtarget.isRV32() && IndexEltVT.bitsGT(XLenVT))
+      IndexVT = IndexVT.changeVectorElementType(XLenVT);
+
+    // If index vector is an i8 vector and the element count exceeds 256, we
+    // should change the element type of index vector to i16 to avoid overflow.
+    if (IndexEltVT == MVT::i8 &&
+        VT.getVectorElementCount().getKnownMinValue() > 256) {
+      // FIXME: We need to do vector splitting manually for LMUL=8 cases.
+      if (getLMUL(IndexVT) == RISCVII::LMUL_8)
+        return SDValue();
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topperc wrote:

Won't returning SDValue() cause crashes code on that didn't crash before? If you return SDValue() here you have to make the type is not legal isLegalExpandLoad so it will get scalarized.

https://github.com/llvm/llvm-project/pull/101954