[llvm] [AArch64] Don't replace dst of SWP instructions with (X|W)ZR (PR #102139)

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git-clang-format --diff 4c6a89710a2580f9784408aae81f73d607d9942d c17af81392df8b5cb9d042b770f44785ad594e4e --extensions cpp -- llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
index 161cf24dd4..cb48e38a6a 100644
--- a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
+++ b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
@@ -108,11 +108,15 @@ static bool atomicReadDroppedOnZero(unsigned Opcode) {
     case AArch64::LDUMINW:    case AArch64::LDUMINX:
     case AArch64::LDUMINLB:   case AArch64::LDUMINLH:
     case AArch64::LDUMINLW:   case AArch64::LDUMINLX:
-    case AArch64::SWPB:       case AArch64::SWPH:
-    case AArch64::SWPW:       case AArch64::SWPX:
-    case AArch64::SWPLB:      case AArch64::SWPLH:
-    case AArch64::SWPLW:      case AArch64::SWPLX:
-    return true;
+    case AArch64::SWPB:
+    case AArch64::SWPH:
+    case AArch64::SWPW:
+    case AArch64::SWPX:
+    case AArch64::SWPLB:
+    case AArch64::SWPLH:
+    case AArch64::SWPLW:
+    case AArch64::SWPLX:
+      return true;
   }
   return false;
 }

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https://github.com/llvm/llvm-project/pull/102139