[llvm] [RISCV] Support llvm.masked.expandload intrinsic (PR #101954)

[Luke Lau via llvm-commits]

================
@@ -10760,16 +10852,51 @@ SDValue RISCVTargetLowering::lowerMaskedLoad(SDValue Op,
   if (!VL)
     VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
 
-  unsigned IntID =
-      IsUnmasked ? Intrinsic::riscv_vle : Intrinsic::riscv_vle_mask;
+  SDValue Index;
+  if (!IsUnmasked && IsExpandingLoad) {
+    MVT IndexVT = ContainerVT;
+    if (ContainerVT.isFloatingPoint())
+      IndexVT = IndexVT.changeVectorElementTypeToInteger();
+
+    MVT IndexEltVT = IndexVT.getVectorElementType();
+    if (Subtarget.isRV32() && IndexEltVT.bitsGT(XLenVT))
+      IndexVT = IndexVT.changeVectorElementType(XLenVT);
+
+    // If index vector is an i8 vector and the element count exceeds 256, we
+    // should change the element type of index vector to i16 to avoid overflow.
+    if (IndexEltVT == MVT::i8 &&
+        VT.getVectorElementCount().getKnownMinValue() > 256) {
+      // If this will result in illegal types, we split it into two loads.
+      if (getLMUL(IndexVT) == RISCVII::LMUL_8)
+        return splitMaskedExpandingLoad(Op, DAG);
----------------
lukel97 wrote:

What do you think about leaving the splitting case for now and just returning SDValue()? Since I think the rest of the PR looks good and we could land that first

Sorry for leading you down a rabbit hole here, I didn't realise it would be this tricky

https://github.com/llvm/llvm-project/pull/101954