[llvm] [RISCV] Support llvm.masked.expandload intrinsic (PR #101954)

[Luke Lau via llvm-commits]

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@@ -10760,16 +10762,38 @@ SDValue RISCVTargetLowering::lowerMaskedLoad(SDValue Op,
   if (!VL)
     VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
 
-  unsigned IntID =
-      IsUnmasked ? Intrinsic::riscv_vle : Intrinsic::riscv_vle_mask;
+  SDValue Index;
+  if (!IsUnmasked && IsExpandingLoad) {
+    MVT IndexVT = ContainerVT;
+    if (ContainerVT.isFloatingPoint())
+      IndexVT = IndexVT.changeVectorElementTypeToInteger();
+
+    if (Subtarget.isRV32() && IndexVT.getVectorElementType().bitsGT(XLenVT))
+      IndexVT = IndexVT.changeVectorElementType(XLenVT);
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lukel97 wrote:

I think the vector shuffle lowering runs into the same issue, it just bails if it can't promote the index to i16

https://github.com/llvm/llvm-project/blob/b1234ddbe2652aa7948242a57107ca7ab12fd2f8/llvm/lib/Target/RISCV/RISCVISelLowering.cpp#L5290-L5297

https://github.com/llvm/llvm-project/pull/101954