[llvm] [NVPTX] Add Volta Atomic SequentiallyConsistent Load and Store Operations (PR #98551)

[via llvm-commits]

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@@ -106,15 +107,30 @@ enum LoadStore {
   isStoreShift = 6
 };
 
-namespace PTXLdStInstCode {
-enum MemorySemantic {
+// Extends LLVM AtomicOrdering with PTX Orderings:
+using OrderingUnderlyingType = unsigned int;
+enum Ordering : OrderingUnderlyingType {
   NotAtomic = 0, // PTX calls these: "Weak"
-  Volatile = 1,
+  // Unordered = 1, // NVPTX maps LLVM Unorderd to Relaxed
   Relaxed = 2,
-  Acquire = 3,
-  Release = 4,
-  RelaxedMMIO = 5
+  // Consume = 3,   // Unimplemented in LLVM; NVPTX would map to "Acquire"
+  Acquire = 4,
+  Release = 5,
+  // AcquireRelease = 6, // TODO
+  SequentiallyConsistent = 7,
+  Volatile = 8,
+  RelaxedMMIO = 9,
+  LAST = RelaxedMMIO
 };
+// Values match LLVM AtomicOrdering for common orderings:
+static_assert(Ordering::NotAtomic == (unsigned)AtomicOrdering::NotAtomic);
+static_assert(Ordering::Relaxed == (unsigned)AtomicOrdering::Monotonic);
+static_assert(Ordering::Acquire == (unsigned)AtomicOrdering::Acquire);
+static_assert(Ordering::Release == (unsigned)AtomicOrdering::Release);
+static_assert(Ordering::SequentiallyConsistent ==
+              (unsigned)AtomicOrdering::SequentiallyConsistent);
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gonzalobg wrote:

I'm going to go with the overkill version proposed above, to unblock this PR. We can always make it less overkill later. 

https://github.com/llvm/llvm-project/pull/98551