[llvm] [RISCV] Support llvm.masked.expandload intrinsic (PR #101954)

[Pengcheng Wang via llvm-commits]

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@@ -10760,16 +10762,38 @@ SDValue RISCVTargetLowering::lowerMaskedLoad(SDValue Op,
   if (!VL)
     VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
 
-  unsigned IntID =
-      IsUnmasked ? Intrinsic::riscv_vle : Intrinsic::riscv_vle_mask;
+  SDValue Index;
+  if (!IsUnmasked && IsExpandingLoad) {
+    MVT IndexVT = ContainerVT;
+    if (ContainerVT.isFloatingPoint())
+      IndexVT = IndexVT.changeVectorElementTypeToInteger();
+
+    if (Subtarget.isRV32() && IndexVT.getVectorElementType().bitsGT(XLenVT))
+      IndexVT = IndexVT.changeVectorElementType(XLenVT);
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wangpc-pp wrote:

> > I tried to split it to small ones but failed.
> 
> What failed?

Well, I may not say it exactly. I just tried to reuse legalizer to split, but it may not be possible. Now I am trying to split it manually in lowering phase.

https://github.com/llvm/llvm-project/pull/101954