[llvm] [RISCV] Support llvm.masked.expandload intrinsic (PR #101954)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 6 00:23:49 PDT 2024
================
@@ -10760,16 +10763,49 @@ SDValue RISCVTargetLowering::lowerMaskedLoad(SDValue Op,
if (!VL)
VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
- unsigned IntID =
- IsUnmasked ? Intrinsic::riscv_vle : Intrinsic::riscv_vle_mask;
+ SDValue Index;
+ if (!IsUnmasked && IsExpandingLoad) {
+ MVT IndexVT = ContainerVT;
+ if (ContainerVT.isFloatingPoint())
+ IndexVT = IndexVT.changeVectorElementTypeToInteger();
+
+ MVT IndexEltVT = IndexVT.getVectorElementType();
+ if (Subtarget.isRV32() && IndexEltVT.bitsGT(XLenVT))
+ IndexVT = IndexVT.changeVectorElementType(XLenVT);
+
+ // If index vector is an i8 vector and the element count exceeds 256, we
+ // should change the element type of index vector to i16 to avoid overflow.
+ if (IndexEltVT == MVT::i8 &&
+ VT.getVectorElementCount().getKnownMinValue() > 256) {
+ // FIXME: Don't know how to make LMUL==8 case legal.
+ assert(getLMUL(IndexVT) != RISCVII::LMUL_8 &&
+ "We don't know how to lower LMUL==8 case");
+ IndexVT = IndexVT.changeVectorElementType(MVT::i16);
+ }
+
+ Index = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
+ DAG.getConstant(Intrinsic::riscv_viota, DL, XLenVT),
----------------
topperc wrote:
getTargetConstant
https://github.com/llvm/llvm-project/pull/101954
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