[llvm] [SPIR-V] Improve test suite pass rate when expensive checks are on (PR #101732)
Vyacheslav Levytskyy via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 5 14:57:35 PDT 2024
https://github.com/VyacheslavLevytskyy updated https://github.com/llvm/llvm-project/pull/101732
>From 8f1974faee06eee5cb8707379725c0f285df87ed Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Fri, 2 Aug 2024 11:35:25 -0700
Subject: [PATCH 1/6] scalar virtual registers have proper bit width
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 28 ++++++++++++++++
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 5 ++-
llvm/test/CodeGen/SPIRV/empty.ll | 5 ++-
llvm/test/CodeGen/SPIRV/transcoding/fadd.ll | 33 +++++++++++++++++--
llvm/test/CodeGen/SPIRV/transcoding/non32.ll | 2 +-
llvm/test/CodeGen/SPIRV/types/or-i1.ll | 2 +-
llvm/test/CodeGen/SPIRV/unnamed-global.ll | 7 ++--
7 files changed, 73 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index ed786bd33aa05..262776deaa049 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -76,6 +76,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
SPIRVGlobalRegistry &GR;
MachineRegisterInfo *MRI;
SyncScopeIDs SSIDs;
+ MachineFunction *HasVRegsReset = nullptr;
/// We need to keep track of the number we give to anonymous global values to
/// generate the same name every time when this is needed.
@@ -101,6 +102,8 @@ class SPIRVInstructionSelector : public InstructionSelector {
#undef GET_GLOBALISEL_TEMPORARIES_DECL
private:
+ void resetVRegsType(MachineFunction &MF);
+
// tblgen-erated 'select' implementation, used as the initial selector for
// the patterns that don't require complex C++.
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
@@ -285,12 +288,37 @@ void SPIRVInstructionSelector::setupMF(MachineFunction &MF, GISelKnownBits *KB,
InstructionSelector::setupMF(MF, KB, CoverageInfo, PSI, BFI);
}
+// To ensure that pattern matching rules are working.
+void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
+ if (HasVRegsReset == &MF)
+ return;
+ HasVRegsReset = &MF;
+
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
+ LLT Ty = MRI.getType(Reg);
+ if (Ty.isScalar()) {
+ unsigned Bits = Ty.getScalarSizeInBits();
+ switch (Bits) {
+ //case 1:
+ case 32:
+ break;
+ default:
+ MRI.setType(Reg, LLT::scalar(32));
+ }
+ }
+ }
+}
+
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI);
// Defined in SPIRVLegalizerInfo.cpp.
extern bool isTypeFoldingSupported(unsigned Opcode);
bool SPIRVInstructionSelector::select(MachineInstr &I) {
+ resetVRegsType(*I.getParent()->getParent());
+
assert(I.getParent() && "Instruction should be in a basic block!");
assert(I.getParent()->getParent() && "Instruction should be in a function!");
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 099557a608185..67ef4fb124125 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -315,7 +315,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
SpvType = GR.getSPIRVTypeForVReg(SrcReg);
assert(SpvType && "VReg is expected to have SPIRV type");
LLT SrcLLT = MRI.getType(SrcReg);
- LLT NewT = LLT::scalar(32);
+ LLT NewT;
bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
bool IsVectorFloat =
SpvType->getOpcode() == SPIRV::OpTypeVector &&
@@ -348,6 +348,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
}
}
} else if (SrcLLT.isVector()) {
+ NewT = LLT::scalar(32); //LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
NewT = LLT::fixed_vector(2, NewT);
if (IsFloat) {
GetIdOp = SPIRV::GET_vfID;
@@ -356,6 +357,8 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
GetIdOp = SPIRV::GET_vID;
DstClass = &SPIRV::vIDRegClass;
}
+ } else {
+ NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
}
Register IdReg = MRI.createGenericVirtualRegister(NewT);
MRI.setRegClass(IdReg, DstClass);
diff --git a/llvm/test/CodeGen/SPIRV/empty.ll b/llvm/test/CodeGen/SPIRV/empty.ll
index 390ab329aea33..29af913a0daee 100644
--- a/llvm/test/CodeGen/SPIRV/empty.ll
+++ b/llvm/test/CodeGen/SPIRV/empty.ll
@@ -1,4 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpCapability Addresses
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll b/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
index af76c0e96f9f4..d84fd492a86a8 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
@@ -8,6 +8,13 @@
; CHECK-SPIRV: OpName %[[#r5:]] "r5"
; CHECK-SPIRV: OpName %[[#r6:]] "r6"
; CHECK-SPIRV: OpName %[[#r7:]] "r7"
+; CHECK-SPIRV: OpName %[[#r1d:]] "r1"
+; CHECK-SPIRV: OpName %[[#r2d:]] "r2"
+; CHECK-SPIRV: OpName %[[#r3d:]] "r3"
+; CHECK-SPIRV: OpName %[[#r4d:]] "r4"
+; CHECK-SPIRV: OpName %[[#r5d:]] "r5"
+; CHECK-SPIRV: OpName %[[#r6d:]] "r6"
+; CHECK-SPIRV: OpName %[[#r7d:]] "r7"
; CHECK-SPIRV-NOT: OpDecorate %[[#r1]] FPFastMathMode
; CHECK-SPIRV-DAG: OpDecorate %[[#r2]] FPFastMathMode NotNaN
; CHECK-SPIRV-DAG: OpDecorate %[[#r3]] FPFastMathMode NotInf
@@ -15,7 +22,9 @@
; CHECK-SPIRV-DAG: OpDecorate %[[#r5]] FPFastMathMode AllowRecip
; CHECK-SPIRV-DAG: OpDecorate %[[#r6]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast
; CHECK-SPIRV-DAG: OpDecorate %[[#r7]] FPFastMathMode NotNaN|NotInf
-; CHECK-SPIRV: %[[#float:]] = OpTypeFloat 32
+; CHECK-SPIRV-DAG: %[[#float:]] = OpTypeFloat 32
+; CHECK-SPIRV-DAG: %[[#double:]] = OpTypeFloat 64
+
; CHECK-SPIRV: %[[#r1]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r2]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r3]] = OpFAdd %[[#float]]
@@ -23,8 +32,7 @@
; CHECK-SPIRV: %[[#r5]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r6]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r7]] = OpFAdd %[[#float]]
-
-define spir_kernel void @testFAdd(float %a, float %b) {
+define spir_kernel void @testFAdd_float(float %a, float %b) {
entry:
%r1 = fadd float %a, %b
%r2 = fadd nnan float %a, %b
@@ -35,3 +43,22 @@ entry:
%r7 = fadd nnan ninf float %a, %b
ret void
}
+
+; CHECK-SPIRV: %[[#r1d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r2d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r3d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r4d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r5d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r6d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r7d]] = OpFAdd %[[#double]]
+define spir_kernel void @testFAdd_double(double %a, double %b) {
+entry:
+ %r1 = fadd double %a, %b
+ %r2 = fadd nnan double %a, %b
+ %r3 = fadd ninf double %a, %b
+ %r4 = fadd nsz double %a, %b
+ %r5 = fadd arcp double %a, %b
+ %r6 = fadd fast double %a, %b
+ %r7 = fadd nnan ninf double %a, %b
+ ret void
+}
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
index d44e32141db75..f3f73ce4fee76 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK: OpTypeInt 16
; CHECK: OpIAdd
diff --git a/llvm/test/CodeGen/SPIRV/types/or-i1.ll b/llvm/test/CodeGen/SPIRV/types/or-i1.ll
index 32dc258d85554..3dda3ff8c3c66 100644
--- a/llvm/test/CodeGen/SPIRV/types/or-i1.ll
+++ b/llvm/test/CodeGen/SPIRV/types/or-i1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#BOOL:]] = OpTypeBool
diff --git a/llvm/test/CodeGen/SPIRV/unnamed-global.ll b/llvm/test/CodeGen/SPIRV/unnamed-global.ll
index d2cd4ea8cafc3..f72334bd7752e 100644
--- a/llvm/test/CodeGen/SPIRV/unnamed-global.ll
+++ b/llvm/test/CodeGen/SPIRV/unnamed-global.ll
@@ -1,5 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
-; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[TyInt:.*]] = OpTypeInt 8 0
; CHECK: %[[ConstInt:.*]] = OpConstant %[[TyInt]] 123
>From 467b6df4ae1986164e0dd2620ed59c5a1bffef1e Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Fri, 2 Aug 2024 12:32:00 -0700
Subject: [PATCH 2/6] improve virtual registers of vector type
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 4 +++
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 27 ++++++++++++-------
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 262776deaa049..6cb68c98ec3aa 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -307,6 +307,10 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
default:
MRI.setType(Reg, LLT::scalar(32));
}
+ } else if (!Ty.isPointer()) {
+ if (auto *Def = MRI.getVRegDef(Reg))
+ if (Def->getOpcode() == SPIRV::ASSIGN_TYPE)
+ MRI.setType(Reg, LLT::scalar(32));
}
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 67ef4fb124125..6323fcfbe8051 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -308,6 +308,14 @@ static void widenScalarLLTNextPow2(Register Reg, MachineRegisterInfo &MRI) {
MRI.setType(Reg, LLT::scalar(NewSz));
}
+inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
+ bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
+ return IsFloat ? true
+ : SpvType->getOpcode() == SPIRV::OpTypeVector &&
+ GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())
+ ->getOpcode() == SPIRV::OpTypeFloat;
+}
+
static std::pair<Register, unsigned>
createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
const SPIRVGlobalRegistry &GR) {
@@ -316,12 +324,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
assert(SpvType && "VReg is expected to have SPIRV type");
LLT SrcLLT = MRI.getType(SrcReg);
LLT NewT;
- bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
- bool IsVectorFloat =
- SpvType->getOpcode() == SPIRV::OpTypeVector &&
- GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())->getOpcode() ==
- SPIRV::OpTypeFloat;
- IsFloat |= IsVectorFloat;
+ bool IsFloat = getIsFloat(SpvType, GR);
auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
auto DstClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
if (SrcLLT.isPointer()) {
@@ -384,8 +387,10 @@ Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy,
if (auto *RC = MRI.getRegClassOrNull(Reg)) {
MRI.setRegClass(NewReg, RC);
} else {
- MRI.setRegClass(NewReg, &SPIRV::IDRegClass);
- MRI.setRegClass(Reg, &SPIRV::IDRegClass);
+ bool IsFloat = false;//getIsFloat(SpirvTy, *GR);
+ auto RegClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
+ MRI.setRegClass(NewReg, RegClass);
+ MRI.setRegClass(Reg, RegClass);
}
GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
// This is to make it convenient for Legalizer to get the SPIRVType
@@ -607,8 +612,10 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
if (UseMI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)
continue;
}
- MRI.setType(DstReg, IsDstPtr ? LLT::pointer(0, GR->getPointerSize())
- : LLT::scalar(32));
+ if (IsDstPtr)
+ MRI.setType(DstReg, LLT::pointer(0, GR->getPointerSize()));
+// MRI.setType(DstReg, IsDstPtr ? LLT::pointer(0, GR->getPointerSize())
+// : LLT::scalar(32));
}
}
}
>From e05c814c50af797f7dc1e293aceb5384cae83ba6 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Mon, 5 Aug 2024 09:44:19 -0700
Subject: [PATCH 3/6] further improvement of virtual register type/class
settings
---
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 14 ++--
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 3 +-
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 21 +++++
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 11 ++-
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 66 ++++++++++++---
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 82 ++++++++++++-------
llvm/test/CodeGen/SPIRV/lshr-constexpr.ll | 22 +++--
.../transcoding/OpVectorInsertDynamic_i16.ll | 36 ++++----
8 files changed, 176 insertions(+), 79 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index e70ddc4d39455..4e779f55aae02 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -214,7 +214,7 @@ SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType,
// TODO: https://github.com/llvm/llvm-project/issues/88129
LLT LLTy = LLT::scalar(32);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
if (MIRBuilder)
assignTypeToVReg(LLVMFloatTy, Res, *MIRBuilder);
else
@@ -354,7 +354,7 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
Register Res = DT.find(ConstFP, &MF);
if (!Res.isValid()) {
Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(32));
- MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ MF.getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, MF);
DT.add(ConstFP, &MF, Res);
@@ -372,7 +372,8 @@ Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
MachineInstr &I,
SPIRVType *SpvType,
const SPIRVInstrInfo &TII,
- unsigned BitWidth) {
+ unsigned BitWidth,
+ bool ZeroAsNull) {
SPIRVType *Type = SpvType;
if (SpvType->getOpcode() == SPIRV::OpTypeVector ||
SpvType->getOpcode() == SPIRV::OpTypeArray) {
@@ -382,12 +383,12 @@ Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
if (Type->getOpcode() == SPIRV::OpTypeFloat) {
SPIRVType *SpvBaseType = getOrCreateSPIRVFloatType(BitWidth, I, TII);
return getOrCreateConstFP(dyn_cast<ConstantFP>(Val)->getValue(), I,
- SpvBaseType, TII);
+ SpvBaseType, TII, ZeroAsNull);
}
assert(Type->getOpcode() == SPIRV::OpTypeInt);
SPIRVType *SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
return getOrCreateConstInt(Val->getUniqueInteger().getSExtValue(), I,
- SpvBaseType, TII);
+ SpvBaseType, TII, ZeroAsNull);
}
Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
@@ -404,7 +405,8 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
// TODO: can moved below once sorting of types/consts/defs is implemented.
Register SpvScalConst;
if (!IsNull)
- SpvScalConst = getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth);
+ SpvScalConst =
+ getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth, ZeroAsNull);
// TODO: handle cases where the type is not 32bit wide
// TODO: https://github.com/llvm/llvm-project/issues/88129
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index 0e26b38225f7a..09377794da8ba 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -440,7 +440,8 @@ class SPIRVGlobalRegistry {
Register getOrCreateBaseRegister(Constant *Val, MachineInstr &I,
SPIRVType *SpvType,
const SPIRVInstrInfo &TII,
- unsigned BitWidth);
+ unsigned BitWidth,
+ bool ZeroAsNull);
Register getOrCreateCompositeOrNull(Constant *Val, MachineInstr &I,
SPIRVType *SpvType,
const SPIRVInstrInfo &TII, Constant *CA,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index ae4e039744286..e8e37c4529d49 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -329,6 +329,27 @@ void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const {
return;
MachineRegisterInfo *MRI = &MF.getRegInfo();
+/*
+ // Try to find redundant copies between virtual registers of the same class.
+ for (MachineBasicBlock &MBB : MF) {
+ if (MBB.empty())
+ continue;
+ bool ReachedBegin = false;
+ for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
+ MachineInstr &MI = *MII;
+ if (MII == Begin)
+ ReachedBegin = true;
+ else
+ --MII;
+ if (MI.getOpcode() != TargetOpcode::COPY)
+ continue;
+ Register SrcReg = MI.getOperand(1).getReg();
+ Register DstReg = MI.getOperand(0).getReg();
+ MRI->replaceRegWith(DstReg, SrcReg);
+ MI.eraseFromParent();
+ }
+ }
+*/
SPIRVGlobalRegistry &GR = *STI.getSPIRVGlobalRegistry();
GR.setCurrentFunc(MF);
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 63549b06e9670..8b472fa6e584a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -242,8 +242,8 @@ def ConstPseudoNull: IntImmLeaf<i64, [{ return Imm.isZero(); }]>;
multiclass IntFPImm<bits<16> opCode, string name> {
def I: Op<opCode, (outs ID:$dst), (ins TYPE:$type, ID:$src, variable_ops),
"$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
- def F: Op<opCode, (outs ID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
- "$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
+ def F: Op<opCode, (outs fID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
+ "$dst = "#name#" $type", [(set fID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
}
def OpConstantTrue: Op<41, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
@@ -258,8 +258,9 @@ def OpConstantComposite: Op<44, (outs ID:$res), (ins TYPE:$type, variable_ops),
def OpConstantSampler: Op<45, (outs ID:$res),
(ins TYPE:$t, SamplerAddressingMode:$s, i32imm:$p, SamplerFilterMode:$f),
"$res = OpConstantSampler $t $s $p $f">;
-def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty",
- [(set ID:$dst, (assigntype ConstPseudoNull, TYPE:$src_ty))]>;
+//def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty",
+// [(set ID:$dst, (assigntype ConstPseudoNull, TYPE:$src_ty))]>;
+def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty">;
def OpSpecConstantTrue: Op<48, (outs ID:$r), (ins TYPE:$t), "$r = OpSpecConstantTrue $t">;
def OpSpecConstantFalse: Op<49, (outs ID:$r), (ins TYPE:$t), "$r = OpSpecConstantFalse $t">;
@@ -471,6 +472,8 @@ def OpConvertBF16ToFINTEL : UnOp<"OpConvertBF16ToFINTEL", 6117>;
def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
"$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
+//def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, ID:$vec, ID:$idx),
+// "$res = OpVectorExtractDynamic $type $vec $idx">;
def OpVectorInsertDynamic: Op<78, (outs ID:$res), (ins TYPE:$ty, ID:$vec, ID:$comp, ID:$idx),
"$res = OpVectorInsertDynamic $ty $vec $comp $idx">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 6cb68c98ec3aa..b794a847963d3 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -294,23 +294,61 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
return;
HasVRegsReset = &MF;
+ /*
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
+ MachineInstr *Def = MRI.getVRegDef(Reg);
+ LLT Ty = MRI.getType(Reg);
+ const TargetRegisterClass *RegClass = MRI.getRegClassOrNull(Reg);
+ if (Ty.isScalar() && (RegClass == &SPIRV::IDRegClass || RegClass ==
+ &SPIRV::ANYIDRegClass)) MRI.setType(Reg, LLT::scalar(32)); if (Def &&
+ Def->getOpcode() == SPIRV::ASSIGN_TYPE) { Register SrcReg =
+ Def->getOperand(1).getReg();
+ //MRI.setType(Reg, LLT::scalar(32));
+ MRI.setType(Reg, MRI.getType(SrcReg));
+ MRI.setRegClass(Reg, &SPIRV::ANYIDRegClass);
+ //MRI.setType(SrcReg, LLT::scalar(32));
+ //MRI.setRegClass(SrcReg, &SPIRV::IDRegClass);
+ } else {
+ //if (Ty.isScalar()) // unsigned Bits = Ty.getScalarSizeInBits();
+ // MRI.setType(Reg, LLT::scalar(32));
+ } // G_FCONSTANT
+ }
+ */
MachineRegisterInfo &MRI = MF.getRegInfo();
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
Register Reg = Register::index2VirtReg(I);
LLT Ty = MRI.getType(Reg);
- if (Ty.isScalar()) {
- unsigned Bits = Ty.getScalarSizeInBits();
- switch (Bits) {
- //case 1:
- case 32:
- break;
- default:
- MRI.setType(Reg, LLT::scalar(32));
- }
- } else if (!Ty.isPointer()) {
- if (auto *Def = MRI.getVRegDef(Reg))
- if (Def->getOpcode() == SPIRV::ASSIGN_TYPE)
+ if (Ty.isScalar())
+ MRI.setType(Reg, LLT::scalar(32));
+ else if (Ty.isVector() && !Ty.isPointer())
+ MRI.setType(Reg, LLT::scalar(32));
+ //MRI.setType(Reg, LLT::fixed_vector(2, LLT::scalar(32)));
+ /* auto *Def = MRI.getVRegDef(Reg));
+ if (!Def)
+ continue;
+ if (Def->getOpcode() == SPIRV::ASSIGN_TYPE) {
+ Register SrcReg = Def->getOperand(1).getReg();
MRI.setType(Reg, LLT::scalar(32));
+ }*/
+ }
+ for (const auto &MBB : MF) {
+ for (const auto &MI : MBB) {
+ if (MI.getOpcode() != SPIRV::ASSIGN_TYPE)
+ continue;
+ Register DstReg = MI.getOperand(0).getReg();
+ LLT DstType = MRI.getType(DstReg);
+ Register SrcReg = MI.getOperand(1).getReg();
+ LLT SrcType = MRI.getType(SrcReg);
+ if (DstType != SrcType)
+ MRI.setType(DstReg, MRI.getType(SrcReg));
+
+ const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
+ const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(SrcReg);
+ if (DstRC != SrcRC && SrcRC)
+ MRI.setRegClass(DstReg, SrcRC);
+ //MRI.setType(Reg, LLT::scalar(32));
}
}
}
@@ -337,10 +375,14 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
if (MRI->getType(DstReg).isPointer())
MRI->setType(DstReg, LLT::scalar(32));
bool Res = selectImpl(I, *CoverageInfo);
+ if (!Res && Def->getOpcode() != TargetOpcode::G_CONSTANT) {
+ I.dump();
+ }
assert(Res || Def->getOpcode() == TargetOpcode::G_CONSTANT);
if (Res)
return Res;
}
+ MRI->setRegClass(DstReg, &SPIRV::IDRegClass);
MRI->replaceRegWith(SrcReg, DstReg);
I.removeFromParent();
return true;
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 6323fcfbe8051..0bc904223f8c5 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -225,17 +225,17 @@ static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR,
static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
MachineRegisterInfo &MRI,
MachineIRBuilder &MIB) {
- SPIRVType *SpirvTy = nullptr;
+ SPIRVType *SpvType = nullptr;
assert(MI && "Machine instr is expected");
if (MI->getOperand(0).isReg()) {
Register Reg = MI->getOperand(0).getReg();
- SpirvTy = GR->getSPIRVTypeForVReg(Reg);
- if (!SpirvTy) {
+ SpvType = GR->getSPIRVTypeForVReg(Reg);
+ if (!SpvType) {
switch (MI->getOpcode()) {
case TargetOpcode::G_CONSTANT: {
MIB.setInsertPt(*MI->getParent(), MI);
Type *Ty = MI->getOperand(1).getCImm()->getType();
- SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB);
+ SpvType = GR->getOrCreateSPIRVType(Ty, MIB);
break;
}
case TargetOpcode::G_GLOBAL_VALUE: {
@@ -244,7 +244,7 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
Type *ElementTy = toTypedPointer(GR->getDeducedGlobalValueType(Global));
auto *Ty = TypedPointerType::get(ElementTy,
Global->getType()->getAddressSpace());
- SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB);
+ SpvType = GR->getOrCreateSPIRVType(Ty, MIB);
break;
}
case TargetOpcode::G_ANYEXT:
@@ -258,17 +258,17 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
unsigned ExpectedBW =
std::max(MRI.getType(Reg).getScalarSizeInBits(), CurrentBW);
unsigned NumElements = GR->getScalarOrVectorComponentCount(Def);
- SpirvTy = GR->getOrCreateSPIRVIntegerType(ExpectedBW, MIB);
+ SpvType = GR->getOrCreateSPIRVIntegerType(ExpectedBW, MIB);
if (NumElements > 1)
- SpirvTy =
- GR->getOrCreateSPIRVVectorType(SpirvTy, NumElements, MIB);
+ SpvType =
+ GR->getOrCreateSPIRVVectorType(SpvType, NumElements, MIB);
}
}
}
break;
}
case TargetOpcode::G_PTRTOINT:
- SpirvTy = GR->getOrCreateSPIRVIntegerType(
+ SpvType = GR->getOrCreateSPIRVIntegerType(
MRI.getType(Reg).getScalarSizeInBits(), MIB);
break;
case TargetOpcode::G_TRUNC:
@@ -278,19 +278,19 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
MachineOperand &Op = MI->getOperand(1);
MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr;
if (Def)
- SpirvTy = propagateSPIRVType(Def, GR, MRI, MIB);
+ SpvType = propagateSPIRVType(Def, GR, MRI, MIB);
break;
}
default:
break;
}
- if (SpirvTy)
- GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
+ if (SpvType)
+ GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
if (!MRI.getRegClassOrNull(Reg))
MRI.setRegClass(Reg, &SPIRV::IDRegClass);
}
}
- return SpirvTy;
+ return SpvType;
}
// To support current approach and limitations wrt. bit width here we widen a
@@ -316,6 +316,30 @@ inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
->getOpcode() == SPIRV::OpTypeFloat;
}
+static const TargetRegisterClass *getRegClass(SPIRVType *SpvType,
+ const SPIRVGlobalRegistry &GR) {
+ unsigned Opcode = SpvType->getOpcode();
+ switch (Opcode) {
+ case SPIRV::OpTypeFloat:
+ return &SPIRV::fIDRegClass;
+ case SPIRV::OpTypePointer:
+ return GR.getPointerSize() == 64 ? &SPIRV::pID64RegClass
+ : &SPIRV::pID32RegClass;
+ case SPIRV::OpTypeVector: {
+ SPIRVType *ElemType =
+ GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
+ unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;
+ if (ElemOpcode == SPIRV::OpTypeFloat)
+ return &SPIRV::vfIDRegClass;
+ if (ElemOpcode == SPIRV::OpTypePointer)
+ return GR.getPointerSize() == 64 ? &SPIRV::vpID64RegClass
+ : &SPIRV::vpID32RegClass;
+ return &SPIRV::vIDRegClass;
+ }
+ }
+ return &SPIRV::IDRegClass;
+}
+
static std::pair<Register, unsigned>
createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
const SPIRVGlobalRegistry &GR) {
@@ -326,7 +350,9 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
LLT NewT;
bool IsFloat = getIsFloat(SpvType, GR);
auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
- auto DstClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
+ auto DstClass =
+ IsFloat ? &SPIRV::fIDRegClass
+ : &SPIRV::IDRegClass; // TODO: call getRegClass(SpvType, GR)
if (SrcLLT.isPointer()) {
unsigned PtrSz = GR.getPointerSize();
NewT = LLT::pointer(0, PtrSz);
@@ -351,8 +377,9 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
}
}
} else if (SrcLLT.isVector()) {
- NewT = LLT::scalar(32); //LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
- NewT = LLT::fixed_vector(2, NewT);
+ NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
+ NewT =
+ LLT::fixed_vector(2, NewT); // TODO: use actual vector size instead of 2
if (IsFloat) {
GetIdOp = SPIRV::GET_vfID;
DstClass = &SPIRV::vfIDRegClass;
@@ -369,40 +396,39 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
}
// Insert ASSIGN_TYPE instuction between Reg and its definition, set NewReg as
-// a dst of the definition, assign SPIRVType to both registers. If SpirvTy is
+// a dst of the definition, assign SPIRVType to both registers. If SpvType is
// provided, use it as SPIRVType in ASSIGN_TYPE, otherwise create it from Ty.
// It's used also in SPIRVBuiltins.cpp.
// TODO: maybe move to SPIRVUtils.
namespace llvm {
-Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy,
+Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpvType,
SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) {
MachineInstr *Def = MRI.getVRegDef(Reg);
- assert((Ty || SpirvTy) && "Either LLVM or SPIRV type is expected.");
+ assert((Ty || SpvType) && "Either LLVM or SPIRV type is expected.");
MIB.setInsertPt(*Def->getParent(),
(Def->getNextNode() ? Def->getNextNode()->getIterator()
: Def->getParent()->end()));
- SpirvTy = SpirvTy ? SpirvTy : GR->getOrCreateSPIRVType(Ty, MIB);
+ SpvType = SpvType ? SpvType : GR->getOrCreateSPIRVType(Ty, MIB);
Register NewReg = MRI.createGenericVirtualRegister(MRI.getType(Reg));
if (auto *RC = MRI.getRegClassOrNull(Reg)) {
MRI.setRegClass(NewReg, RC);
} else {
- bool IsFloat = false;//getIsFloat(SpirvTy, *GR);
- auto RegClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
+ auto RegClass = getRegClass(SpvType, *GR);
MRI.setRegClass(NewReg, RegClass);
MRI.setRegClass(Reg, RegClass);
}
- GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
+ GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
// This is to make it convenient for Legalizer to get the SPIRVType
// when processing the actual MI (i.e. not pseudo one).
- GR->assignSPIRVTypeToVReg(SpirvTy, NewReg, MIB.getMF());
+ GR->assignSPIRVTypeToVReg(SpvType, NewReg, MIB.getMF());
// Copy MIFlags from Def to ASSIGN_TYPE instruction. It's required to keep
// the flags after instruction selection.
const uint32_t Flags = Def->getFlags();
MIB.buildInstr(SPIRV::ASSIGN_TYPE)
.addDef(Reg)
.addUse(NewReg)
- .addUse(GR->getSPIRVTypeID(SpirvTy))
+ .addUse(GR->getSPIRVTypeID(SpvType))
.setMIFlags(Flags);
Def->getOperand(0).setReg(NewReg);
return NewReg;
@@ -603,8 +629,8 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
Register DstReg = MI.getOperand(0).getReg();
bool IsDstPtr = MRI.getType(DstReg).isPointer();
bool isDstVec = MRI.getType(DstReg).isVector();
- if (IsDstPtr || isDstVec)
- MRI.setRegClass(DstReg, &SPIRV::IDRegClass);
+// if (IsDstPtr || isDstVec)
+// MRI.setRegClass(DstReg, &SPIRV::IDRegClass);
// Don't need to reset type of register holding constant and used in
// G_ADDRSPACE_CAST, since it breaks legalizer.
if (Opcode == TargetOpcode::G_CONSTANT && MRI.hasOneUse(DstReg)) {
@@ -614,8 +640,6 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
}
if (IsDstPtr)
MRI.setType(DstReg, LLT::pointer(0, GR->getPointerSize()));
-// MRI.setType(DstReg, IsDstPtr ? LLT::pointer(0, GR->getPointerSize())
-// : LLT::scalar(32));
}
}
}
diff --git a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
index 44b11f3ddb273..f2f97f56263f9 100644
--- a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
+++ b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
@@ -1,14 +1,18 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV-DAG: %[[#type_int32:]] = OpTypeInt 32 0
-; CHECK-SPIRV-DAG: %[[#type_int64:]] = OpTypeInt 64 0
-; CHECK-SPIRV: %[[#type_vec:]] = OpTypeVector %[[#type_int32]] 2
-; CHECK-SPIRV: %[[#const1:]] = OpConstant %[[#type_int32]] 1
-; CHECK-SPIRV: %[[#vec_const:]] = OpConstantComposite %[[#type_vec]] %[[#const1]] %[[#const1]]
-; CHECK-SPIRV: %[[#const32:]] = OpConstant %[[#type_int64]] 32
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV: %[[#bitcast_res:]] = OpBitcast %[[#type_int64]] %[[#vec_const]]
-; CHECK-SPIRV: %[[#shift_res:]] = OpShiftRightLogical %[[#type_int64]] %[[#bitcast_res]] %[[#const32]]
+; CHECK-DAG: %[[#type_int32:]] = OpTypeInt 32 0
+; CHECK-DAG: %[[#type_int64:]] = OpTypeInt 64 0
+; CHECK-DAG: %[[#type_vec:]] = OpTypeVector %[[#type_int32]] 2
+; CHECK-DAG: %[[#const1:]] = OpConstant %[[#type_int32]] 1
+; CHECK-DAG: %[[#vec_const:]] = OpConstantComposite %[[#type_vec]] %[[#const1]] %[[#const1]]
+; CHECK-DAG: %[[#const32:]] = OpConstant %[[#type_int64]] 32
+
+; CHECK: %[[#bitcast_res:]] = OpBitcast %[[#type_int64]] %[[#vec_const]]
+; CHECK: %[[#shift_res:]] = OpShiftRightLogical %[[#type_int64]] %[[#bitcast_res]] %[[#const32]]
define void @foo(i64* %arg) {
entry:
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
index cb41aad2a0c5f..0e66f2d22a3ff 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
@@ -1,23 +1,23 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV: OpName %[[#v:]] "v"
-; CHECK-SPIRV: OpName %[[#index:]] "index"
-; CHECK-SPIRV: OpName %[[#res:]] "res"
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV-DAG: %[[#int16:]] = OpTypeInt 16
-; CHECK-SPIRV-DAG: %[[#int32:]] = OpTypeInt 32
-; CHECK-SPIRV-DAG: %[[#int16_2:]] = OpTypeVector %[[#int16]] 2
-
-; CHECK-SPIRV: %[[#undef:]] = OpUndef %[[#int16_2]]
-
-; CHECK-SPIRV-DAG: %[[#const1:]] = OpConstant %[[#int16]] 4
-; CHECK-SPIRV-DAG: %[[#const2:]] = OpConstant %[[#int16]] 8
-; CHECK-SPIRV-NOT: %[[#idx1:]] = OpConstant %[[#int32]] 0
-; CHECK-SPIRV-NOT: %[[#idx2:]] = OpConstant %[[#int32]] 1
-
-; CHECK-SPIRV: %[[#vec1:]] = OpCompositeInsert %[[#int16_2]] %[[#const1]] %[[#undef]] 0
-; CHECK-SPIRV: %[[#vec2:]] = OpCompositeInsert %[[#int16_2]] %[[#const2]] %[[#vec1]] 1
-; CHECK-SPIRV: %[[#res]] = OpVectorInsertDynamic %[[#int16_2]] %[[#vec2]] %[[#v]] %[[#index]]
+; CHECK: OpName %[[#v:]] "v"
+; CHECK: OpName %[[#index:]] "index"
+; CHECK: OpName %[[#res:]] "res"
+; CHECK-DAG: %[[#int16:]] = OpTypeInt 16
+; CHECK-DAG: %[[#int32:]] = OpTypeInt 32
+; CHECK-DAG: %[[#int16_2:]] = OpTypeVector %[[#int16]] 2
+; CHECK-DAG: %[[#undef:]] = OpUndef %[[#int16_2]]
+; CHECK-DAG: %[[#const1:]] = OpConstant %[[#int16]] 4
+; CHECK-DAG: %[[#const2:]] = OpConstant %[[#int16]] 8
+; CHECK-NOT: %[[#idx1:]] = OpConstant %[[#int32]] 0
+; CHECK-NOT: %[[#idx2:]] = OpConstant %[[#int32]] 1
+; CHECK: %[[#vec1:]] = OpCompositeInsert %[[#int16_2]] %[[#const1]] %[[#undef]] 0
+; CHECK: %[[#vec2:]] = OpCompositeInsert %[[#int16_2]] %[[#const2]] %[[#vec1]] 1
+; CHECK: %[[#res]] = OpVectorInsertDynamic %[[#int16_2]] %[[#vec2]] %[[#v]] %[[#index]]
define spir_kernel void @test(<2 x i16>* nocapture %out, i16 %v, i32 %index) {
entry:
>From 21016312dd895e8261554a62c17f520b2568cb65 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Mon, 5 Aug 2024 12:40:12 -0700
Subject: [PATCH 4/6] fix emission of definitions
---
.../SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp | 3 +--
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 22 +------------------
2 files changed, 2 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
index 8aea26d9963ce..6dd0df2a104c0 100644
--- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp
@@ -67,8 +67,7 @@ static bool hasType(const MCInst &MI, const MCInstrInfo &MII) {
// Check if we define an ID, and take a type as operand 1.
auto &DefOpInfo = MCDesc.operands()[0];
auto &FirstArgOpInfo = MCDesc.operands()[1];
- return (DefOpInfo.RegClass == SPIRV::IDRegClassID ||
- DefOpInfo.RegClass == SPIRV::ANYIDRegClassID) &&
+ return DefOpInfo.RegClass != SPIRV::TYPERegClassID &&
FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID;
}
return false;
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index e8e37c4529d49..dc9f5723cba6b 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -329,27 +329,6 @@ void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const {
return;
MachineRegisterInfo *MRI = &MF.getRegInfo();
-/*
- // Try to find redundant copies between virtual registers of the same class.
- for (MachineBasicBlock &MBB : MF) {
- if (MBB.empty())
- continue;
- bool ReachedBegin = false;
- for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
- MachineInstr &MI = *MII;
- if (MII == Begin)
- ReachedBegin = true;
- else
- --MII;
- if (MI.getOpcode() != TargetOpcode::COPY)
- continue;
- Register SrcReg = MI.getOperand(1).getReg();
- Register DstReg = MI.getOperand(0).getReg();
- MRI->replaceRegWith(DstReg, SrcReg);
- MI.eraseFromParent();
- }
- }
-*/
SPIRVGlobalRegistry &GR = *STI.getSPIRVGlobalRegistry();
GR.setCurrentFunc(MF);
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
@@ -357,6 +336,7 @@ void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const {
for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
MBBI != MBBE;) {
MachineInstr &MI = *MBBI++;
+ MI.dump();
switch (MI.getOpcode()) {
case SPIRV::OpAtomicLoad:
case SPIRV::OpAtomicExchange:
>From 877a8f65518c1e3a063ff427ed6def1e326c674d Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Mon, 5 Aug 2024 13:03:02 -0700
Subject: [PATCH 5/6] code formatting; harden tests
---
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 9 ++--
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 3 +-
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 1 -
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 4 --
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 36 +--------------
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 45 ++++---------------
llvm/test/CodeGen/SPIRV/transcoding/non32.ll | 6 ++-
7 files changed, 19 insertions(+), 85 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 4e779f55aae02..3ee355a913bf9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -368,12 +368,9 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
return Res;
}
-Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
- MachineInstr &I,
- SPIRVType *SpvType,
- const SPIRVInstrInfo &TII,
- unsigned BitWidth,
- bool ZeroAsNull) {
+Register SPIRVGlobalRegistry::getOrCreateBaseRegister(
+ Constant *Val, MachineInstr &I, SPIRVType *SpvType,
+ const SPIRVInstrInfo &TII, unsigned BitWidth, bool ZeroAsNull) {
SPIRVType *Type = SpvType;
if (SpvType->getOpcode() == SPIRV::OpTypeVector ||
SpvType->getOpcode() == SPIRV::OpTypeArray) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index 09377794da8ba..821c1218fcb7f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -439,8 +439,7 @@ class SPIRVGlobalRegistry {
SPIRVType *finishCreatingSPIRVType(const Type *LLVMTy, SPIRVType *SpirvType);
Register getOrCreateBaseRegister(Constant *Val, MachineInstr &I,
SPIRVType *SpvType,
- const SPIRVInstrInfo &TII,
- unsigned BitWidth,
+ const SPIRVInstrInfo &TII, unsigned BitWidth,
bool ZeroAsNull);
Register getOrCreateCompositeOrNull(Constant *Val, MachineInstr &I,
SPIRVType *SpvType,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index dc9f5723cba6b..ae4e039744286 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -336,7 +336,6 @@ void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const {
for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
MBBI != MBBE;) {
MachineInstr &MI = *MBBI++;
- MI.dump();
switch (MI.getOpcode()) {
case SPIRV::OpAtomicLoad:
case SPIRV::OpAtomicExchange:
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 8b472fa6e584a..9d06711204edc 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -258,8 +258,6 @@ def OpConstantComposite: Op<44, (outs ID:$res), (ins TYPE:$type, variable_ops),
def OpConstantSampler: Op<45, (outs ID:$res),
(ins TYPE:$t, SamplerAddressingMode:$s, i32imm:$p, SamplerFilterMode:$f),
"$res = OpConstantSampler $t $s $p $f">;
-//def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty",
-// [(set ID:$dst, (assigntype ConstPseudoNull, TYPE:$src_ty))]>;
def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty">;
def OpSpecConstantTrue: Op<48, (outs ID:$r), (ins TYPE:$t), "$r = OpSpecConstantTrue $t">;
@@ -472,8 +470,6 @@ def OpConvertBF16ToFINTEL : UnOp<"OpConvertBF16ToFINTEL", 6117>;
def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
"$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
-//def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, ID:$vec, ID:$idx),
-// "$res = OpVectorExtractDynamic $type $vec $idx">;
def OpVectorInsertDynamic: Op<78, (outs ID:$res), (ins TYPE:$ty, ID:$vec, ID:$comp, ID:$idx),
"$res = OpVectorInsertDynamic $ty $vec $comp $idx">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index b794a847963d3..84c8491c6b7c8 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -288,34 +288,12 @@ void SPIRVInstructionSelector::setupMF(MachineFunction &MF, GISelKnownBits *KB,
InstructionSelector::setupMF(MF, KB, CoverageInfo, PSI, BFI);
}
-// To ensure that pattern matching rules are working.
+// Ensure that register classes correspond to pattern matching rules.
void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
if (HasVRegsReset == &MF)
return;
HasVRegsReset = &MF;
- /*
- MachineRegisterInfo &MRI = MF.getRegInfo();
- for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
- Register Reg = Register::index2VirtReg(I);
- MachineInstr *Def = MRI.getVRegDef(Reg);
- LLT Ty = MRI.getType(Reg);
- const TargetRegisterClass *RegClass = MRI.getRegClassOrNull(Reg);
- if (Ty.isScalar() && (RegClass == &SPIRV::IDRegClass || RegClass ==
- &SPIRV::ANYIDRegClass)) MRI.setType(Reg, LLT::scalar(32)); if (Def &&
- Def->getOpcode() == SPIRV::ASSIGN_TYPE) { Register SrcReg =
- Def->getOperand(1).getReg();
- //MRI.setType(Reg, LLT::scalar(32));
- MRI.setType(Reg, MRI.getType(SrcReg));
- MRI.setRegClass(Reg, &SPIRV::ANYIDRegClass);
- //MRI.setType(SrcReg, LLT::scalar(32));
- //MRI.setRegClass(SrcReg, &SPIRV::IDRegClass);
- } else {
- //if (Ty.isScalar()) // unsigned Bits = Ty.getScalarSizeInBits();
- // MRI.setType(Reg, LLT::scalar(32));
- } // G_FCONSTANT
- }
- */
MachineRegisterInfo &MRI = MF.getRegInfo();
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
Register Reg = Register::index2VirtReg(I);
@@ -324,14 +302,6 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
MRI.setType(Reg, LLT::scalar(32));
else if (Ty.isVector() && !Ty.isPointer())
MRI.setType(Reg, LLT::scalar(32));
- //MRI.setType(Reg, LLT::fixed_vector(2, LLT::scalar(32)));
- /* auto *Def = MRI.getVRegDef(Reg));
- if (!Def)
- continue;
- if (Def->getOpcode() == SPIRV::ASSIGN_TYPE) {
- Register SrcReg = Def->getOperand(1).getReg();
- MRI.setType(Reg, LLT::scalar(32));
- }*/
}
for (const auto &MBB : MF) {
for (const auto &MI : MBB) {
@@ -348,7 +318,6 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(SrcReg);
if (DstRC != SrcRC && SrcRC)
MRI.setRegClass(DstReg, SrcRC);
- //MRI.setType(Reg, LLT::scalar(32));
}
}
}
@@ -375,9 +344,6 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
if (MRI->getType(DstReg).isPointer())
MRI->setType(DstReg, LLT::scalar(32));
bool Res = selectImpl(I, *CoverageInfo);
- if (!Res && Def->getOpcode() != TargetOpcode::G_CONSTANT) {
- I.dump();
- }
assert(Res || Def->getOpcode() == TargetOpcode::G_CONSTANT);
if (Res)
return Res;
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 0bc904223f8c5..3ff0a8e1125ad 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -346,52 +346,29 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
if (!SpvType)
SpvType = GR.getSPIRVTypeForVReg(SrcReg);
assert(SpvType && "VReg is expected to have SPIRV type");
- LLT SrcLLT = MRI.getType(SrcReg);
LLT NewT;
+ LLT SrcLLT = MRI.getType(SrcReg);
bool IsFloat = getIsFloat(SpvType, GR);
auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
- auto DstClass =
- IsFloat ? &SPIRV::fIDRegClass
- : &SPIRV::IDRegClass; // TODO: call getRegClass(SpvType, GR)
if (SrcLLT.isPointer()) {
unsigned PtrSz = GR.getPointerSize();
NewT = LLT::pointer(0, PtrSz);
bool IsVec = SrcLLT.isVector();
if (IsVec)
NewT = LLT::fixed_vector(2, NewT);
- if (PtrSz == 64) {
- if (IsVec) {
- GetIdOp = SPIRV::GET_vpID64;
- DstClass = &SPIRV::vpID64RegClass;
- } else {
- GetIdOp = SPIRV::GET_pID64;
- DstClass = &SPIRV::pID64RegClass;
- }
- } else {
- if (IsVec) {
- GetIdOp = SPIRV::GET_vpID32;
- DstClass = &SPIRV::vpID32RegClass;
- } else {
- GetIdOp = SPIRV::GET_pID32;
- DstClass = &SPIRV::pID32RegClass;
- }
- }
+ if (PtrSz == 64)
+ GetIdOp = IsVec ? SPIRV::GET_vpID64 : SPIRV::GET_pID64;
+ else
+ GetIdOp = IsVec ? SPIRV::GET_vpID32 : SPIRV::GET_pID32;
} else if (SrcLLT.isVector()) {
NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
- NewT =
- LLT::fixed_vector(2, NewT); // TODO: use actual vector size instead of 2
- if (IsFloat) {
- GetIdOp = SPIRV::GET_vfID;
- DstClass = &SPIRV::vfIDRegClass;
- } else {
- GetIdOp = SPIRV::GET_vID;
- DstClass = &SPIRV::vIDRegClass;
- }
+ NewT = LLT::fixed_vector(2, NewT);
+ GetIdOp = IsFloat ? SPIRV::GET_vfID : SPIRV::GET_vID;
} else {
NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
}
Register IdReg = MRI.createGenericVirtualRegister(NewT);
- MRI.setRegClass(IdReg, DstClass);
+ MRI.setRegClass(IdReg, getRegClass(SpvType, GR));
return {IdReg, GetIdOp};
}
@@ -627,10 +604,6 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
if (!isTypeFoldingSupported(Opcode))
continue;
Register DstReg = MI.getOperand(0).getReg();
- bool IsDstPtr = MRI.getType(DstReg).isPointer();
- bool isDstVec = MRI.getType(DstReg).isVector();
-// if (IsDstPtr || isDstVec)
-// MRI.setRegClass(DstReg, &SPIRV::IDRegClass);
// Don't need to reset type of register holding constant and used in
// G_ADDRSPACE_CAST, since it breaks legalizer.
if (Opcode == TargetOpcode::G_CONSTANT && MRI.hasOneUse(DstReg)) {
@@ -638,7 +611,7 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
if (UseMI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)
continue;
}
- if (IsDstPtr)
+ if (MRI.getType(DstReg).isPointer())
MRI.setType(DstReg, LLT::pointer(0, GR->getPointerSize()));
}
}
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
index f3f73ce4fee76..790bf406ff531 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
@@ -1,4 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpTypeInt 16
; CHECK: OpIAdd
>From ff280bd266062c786d5d77d8a04f84b3cf722aba Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Mon, 5 Aug 2024 14:57:22 -0700
Subject: [PATCH 6/6] add a superclass for id virtual register classes
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 154 +++++++++---------
llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp | 8 +-
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 14 +-
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 8 +-
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 56 ++++---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 30 ++--
llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp | 6 +-
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 10 +-
llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td | 2 +-
llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td | 10 +-
llvm/test/CodeGen/SPIRV/atomicrmw.ll | 6 +-
11 files changed, 158 insertions(+), 146 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 1609576c038d0..c759fdcbd0a1e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -408,7 +408,7 @@ buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType,
Register ResultRegister =
MIRBuilder.getMRI()->createGenericVirtualRegister(Type);
- MIRBuilder.getMRI()->setRegClass(ResultRegister, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(ResultRegister, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(BoolType, ResultRegister, MIRBuilder.getMF());
return std::make_tuple(ResultRegister, BoolType);
}
@@ -442,7 +442,7 @@ static Register buildLoadInst(SPIRVType *BaseType, Register PtrRegister,
Register DestinationReg = Register(0)) {
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
if (!DestinationReg.isValid()) {
- DestinationReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ DestinationReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
MRI->setType(DestinationReg, LLT::scalar(32));
GR->assignSPIRVTypeToVReg(BaseType, DestinationReg, MIRBuilder.getMF());
}
@@ -460,7 +460,7 @@ static Register buildBuiltinVariableLoad(
SPIRVGlobalRegistry *GR, SPIRV::BuiltIn::BuiltIn BuiltinValue, LLT LLType,
Register Reg = Register(0), bool isConst = true, bool hasLinkageTy = true) {
Register NewRegister =
- MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
MIRBuilder.getMRI()->setType(NewRegister,
LLT::pointer(0, GR->getPointerSize()));
SPIRVType *PtrType = GR->getOrCreateSPIRVPointerType(
@@ -544,7 +544,7 @@ static Register buildScopeReg(Register CLScopeRegister,
Scope = getSPIRVScope(CLScope);
if (CLScope == static_cast<unsigned>(Scope)) {
- MRI->setRegClass(CLScopeRegister, &SPIRV::IDRegClass);
+ MRI->setRegClass(CLScopeRegister, &SPIRV::iIDRegClass);
return CLScopeRegister;
}
}
@@ -564,7 +564,7 @@ static Register buildMemSemanticsReg(Register SemanticsRegister,
getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister));
if (Order == Semantics) {
- MRI->setRegClass(SemanticsRegister, &SPIRV::IDRegClass);
+ MRI->setRegClass(SemanticsRegister, &SPIRV::iIDRegClass);
return SemanticsRegister;
}
}
@@ -583,7 +583,7 @@ static bool buildOpFromWrapper(MachineIRBuilder &MIRBuilder, unsigned Opcode,
for (unsigned i = 0; i < Sz; ++i) {
Register ArgReg = Call->Arguments[i];
if (!MRI->getRegClassOrNull(ArgReg))
- MRI->setRegClass(ArgReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ArgReg, &SPIRV::iIDRegClass);
MIB.addUse(ArgReg);
}
for (uint32_t ImmArg : ImmArgs)
@@ -599,8 +599,8 @@ static bool buildAtomicInitInst(const SPIRV::IncomingCall *Call,
assert(Call->Arguments.size() == 2 &&
"Need 2 arguments for atomic init translation");
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpStore)
.addUse(Call->Arguments[0])
.addUse(Call->Arguments[1]);
@@ -616,14 +616,14 @@ static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call,
return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicLoad, Call, TypeReg);
Register PtrRegister = Call->Arguments[0];
- MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::iIDRegClass);
// TODO: if true insert call to __translate_ocl_memory_sccope before
// OpAtomicLoad and the function implementation. We can use Translator's
// output for transcoding/atomic_explicit_arguments.cl as an example.
Register ScopeRegister;
if (Call->Arguments.size() > 1) {
ScopeRegister = Call->Arguments[1];
- MIRBuilder.getMRI()->setRegClass(ScopeRegister, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(ScopeRegister, &SPIRV::iIDRegClass);
} else
ScopeRegister = buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR);
@@ -631,7 +631,7 @@ static bool buildAtomicLoadInst(const SPIRV::IncomingCall *Call,
if (Call->Arguments.size() > 2) {
// TODO: Insert call to __translate_ocl_memory_order before OpAtomicLoad.
MemSemanticsReg = Call->Arguments[2];
- MIRBuilder.getMRI()->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
} else {
int Semantics =
SPIRV::MemorySemantics::SequentiallyConsistent |
@@ -658,12 +658,12 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
Register ScopeRegister =
buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR);
Register PtrRegister = Call->Arguments[0];
- MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::iIDRegClass);
int Semantics =
SPIRV::MemorySemantics::SequentiallyConsistent |
getMemSemanticsForStorageClass(GR->getPointerStorageClass(PtrRegister));
Register MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GR);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpAtomicStore)
.addUse(PtrRegister)
.addUse(ScopeRegister)
@@ -686,9 +686,9 @@ static bool buildAtomicCompareExchangeInst(
Register ObjectPtr = Call->Arguments[0]; // Pointer (volatile A *object.)
Register ExpectedArg = Call->Arguments[1]; // Comparator (C* expected).
Register Desired = Call->Arguments[2]; // Value (C Desired).
- MRI->setRegClass(ObjectPtr, &SPIRV::IDRegClass);
- MRI->setRegClass(ExpectedArg, &SPIRV::IDRegClass);
- MRI->setRegClass(Desired, &SPIRV::IDRegClass);
+ MRI->setRegClass(ObjectPtr, &SPIRV::iIDRegClass);
+ MRI->setRegClass(ExpectedArg, &SPIRV::iIDRegClass);
+ MRI->setRegClass(Desired, &SPIRV::iIDRegClass);
SPIRVType *SpvDesiredTy = GR->getSPIRVTypeForVReg(Desired);
LLT DesiredLLT = MRI->getType(Desired);
@@ -729,8 +729,8 @@ static bool buildAtomicCompareExchangeInst(
MemSemEqualReg = Call->Arguments[3];
if (MemOrdNeq == MemSemEqual)
MemSemUnequalReg = Call->Arguments[4];
- MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
- MRI->setRegClass(Call->Arguments[4], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[3], &SPIRV::iIDRegClass);
+ MRI->setRegClass(Call->Arguments[4], &SPIRV::iIDRegClass);
}
if (!MemSemEqualReg.isValid())
MemSemEqualReg = buildConstantIntReg(MemSemEqual, MIRBuilder, GR);
@@ -747,7 +747,7 @@ static bool buildAtomicCompareExchangeInst(
Scope = getSPIRVScope(ClScope);
if (ClScope == static_cast<unsigned>(Scope))
ScopeReg = Call->Arguments[5];
- MRI->setRegClass(Call->Arguments[5], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[5], &SPIRV::iIDRegClass);
}
if (!ScopeReg.isValid())
ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GR);
@@ -760,7 +760,7 @@ static bool buildAtomicCompareExchangeInst(
Register Tmp = !IsCmpxchg ? MRI->createGenericVirtualRegister(DesiredLLT)
: Call->ReturnRegister;
if (!MRI->getRegClassOrNull(Tmp))
- MRI->setRegClass(Tmp, &SPIRV::IDRegClass);
+ MRI->setRegClass(Tmp, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(SpvDesiredTy, Tmp, MIRBuilder.getMF());
SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder);
@@ -799,12 +799,12 @@ static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
Register PtrRegister = Call->Arguments[0];
unsigned Semantics = SPIRV::MemorySemantics::None;
- MRI->setRegClass(PtrRegister, &SPIRV::IDRegClass);
+ MRI->setRegClass(PtrRegister, &SPIRV::iIDRegClass);
Register MemSemanticsReg =
Call->Arguments.size() >= 3 ? Call->Arguments[2] : Register();
MemSemanticsReg = buildMemSemanticsReg(MemSemanticsReg, PtrRegister,
Semantics, MIRBuilder, GR);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
Register ValueReg = Call->Arguments[1];
Register ValueTypeReg = GR->getSPIRVTypeID(Call->ReturnType);
// support cl_ext_float_atomics
@@ -817,7 +817,7 @@ static bool buildAtomicRMWInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
Opcode = SPIRV::OpAtomicFAddEXT;
Register NegValueReg =
MRI->createGenericVirtualRegister(MRI->getType(ValueReg));
- MRI->setRegClass(NegValueReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(NegValueReg, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(Call->ReturnType, NegValueReg,
MIRBuilder.getMF());
MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
@@ -849,16 +849,16 @@ static bool buildAtomicFloatingRMWInst(const SPIRV::IncomingCall *Call,
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register PtrReg = Call->Arguments[0];
- MRI->setRegClass(PtrReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(PtrReg, &SPIRV::iIDRegClass);
Register ScopeReg = Call->Arguments[1];
- MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
Register MemSemanticsReg = Call->Arguments[2];
- MRI->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
Register ValueReg = Call->Arguments[3];
- MRI->setRegClass(ValueReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ValueReg, &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(Opcode)
.addDef(Call->ReturnRegister)
@@ -939,7 +939,7 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
Register MemSemanticsReg;
if (MemFlags == MemSemantics) {
MemSemanticsReg = Call->Arguments[0];
- MRI->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(MemSemanticsReg, &SPIRV::iIDRegClass);
} else
MemSemanticsReg = buildConstantIntReg(MemSemantics, MIRBuilder, GR);
@@ -962,7 +962,7 @@ static bool buildBarrierInst(const SPIRV::IncomingCall *Call, unsigned Opcode,
if (CLScope == static_cast<unsigned>(Scope)) {
ScopeReg = Call->Arguments[1];
- MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
}
}
@@ -1074,7 +1074,7 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
uint64_t GrpOp = MI->getOperand(1).getCImm()->getValue().getZExtValue();
Register ScopeReg = Call->Arguments[0];
if (!MRI->getRegClassOrNull(ScopeReg))
- MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
auto MIB = MIRBuilder.buildInstr(GroupBuiltin->Opcode)
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType))
@@ -1083,7 +1083,7 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
for (unsigned i = 2; i < Call->Arguments.size(); ++i) {
Register ArgReg = Call->Arguments[i];
if (!MRI->getRegClassOrNull(ArgReg))
- MRI->setRegClass(ArgReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ArgReg, &SPIRV::iIDRegClass);
MIB.addUse(ArgReg);
}
return true;
@@ -1131,10 +1131,10 @@ static bool generateGroupInst(const SPIRV::IncomingCall *Call,
MIB.addImm(GroupBuiltin->GroupOperation);
if (Call->Arguments.size() > 0) {
MIB.addUse(Arg0.isValid() ? Arg0 : Call->Arguments[0]);
- MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
for (unsigned i = 1; i < Call->Arguments.size(); i++) {
MIB.addUse(Call->Arguments[i]);
- MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[i], &SPIRV::iIDRegClass);
}
}
@@ -1208,7 +1208,7 @@ static bool generateIntelSubgroupsInst(const SPIRV::IncomingCall *Call,
.addUse(GR->getSPIRVTypeID(Call->ReturnType));
for (size_t i = 0; i < Call->Arguments.size(); ++i) {
MIB.addUse(Call->Arguments[i]);
- MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[i], &SPIRV::iIDRegClass);
}
return true;
@@ -1232,11 +1232,11 @@ static bool generateGroupUniformInst(const SPIRV::IncomingCall *Call,
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register GroupResultReg = Call->ReturnRegister;
- MRI->setRegClass(GroupResultReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(GroupResultReg, &SPIRV::iIDRegClass);
// Scope
Register ScopeReg = Call->Arguments[0];
- MRI->setRegClass(ScopeReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ScopeReg, &SPIRV::iIDRegClass);
// Group Operation
Register ConstGroupOpReg = Call->Arguments[1];
@@ -1253,7 +1253,7 @@ static bool generateGroupUniformInst(const SPIRV::IncomingCall *Call,
// Value
Register ValueReg = Call->Arguments[2];
- MRI->setRegClass(ValueReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ValueReg, &SPIRV::iIDRegClass);
auto MIB = MIRBuilder.buildInstr(GroupUniform->Opcode)
.addDef(GroupResultReg)
@@ -1280,7 +1280,7 @@ static bool generateKernelClockInst(const SPIRV::IncomingCall *Call,
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register ResultReg = Call->ReturnRegister;
- MRI->setRegClass(ResultReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ResultReg, &SPIRV::iIDRegClass);
// Deduce the `Scope` operand from the builtin function name.
SPIRV::Scope::Scope ScopeArg =
@@ -1350,7 +1350,7 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call,
Register DefaultReg = Call->ReturnRegister;
if (PointerSize != ResultWidth) {
DefaultReg = MRI->createGenericVirtualRegister(LLT::scalar(PointerSize));
- MRI->setRegClass(DefaultReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(DefaultReg, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(PointerSizeType, DefaultReg,
MIRBuilder.getMF());
ToTruncate = DefaultReg;
@@ -1368,7 +1368,7 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call,
Register Extracted = Call->ReturnRegister;
if (!IsConstantIndex || PointerSize != ResultWidth) {
Extracted = MRI->createGenericVirtualRegister(LLT::scalar(PointerSize));
- MRI->setRegClass(Extracted, &SPIRV::IDRegClass);
+ MRI->setRegClass(Extracted, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(PointerSizeType, Extracted, MIRBuilder.getMF());
}
// Use Intrinsic::spv_extractelt so dynamic vs static extraction is
@@ -1387,7 +1387,7 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call,
Register CompareRegister =
MRI->createGenericVirtualRegister(LLT::scalar(1));
- MRI->setRegClass(CompareRegister, &SPIRV::IDRegClass);
+ MRI->setRegClass(CompareRegister, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(BoolType, CompareRegister, MIRBuilder.getMF());
// Use G_ICMP to check if idxVReg < 3.
@@ -1404,7 +1404,7 @@ static bool genWorkgroupQuery(const SPIRV::IncomingCall *Call,
if (PointerSize != ResultWidth) {
SelectionResult =
MRI->createGenericVirtualRegister(LLT::scalar(PointerSize));
- MRI->setRegClass(SelectionResult, &SPIRV::IDRegClass);
+ MRI->setRegClass(SelectionResult, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(PointerSizeType, SelectionResult,
MIRBuilder.getMF());
}
@@ -1588,7 +1588,7 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call,
if (NumExpectedRetComponents != NumActualRetComponents) {
QueryResult = MIRBuilder.getMRI()->createGenericVirtualRegister(
LLT::fixed_vector(NumActualRetComponents, 32));
- MIRBuilder.getMRI()->setRegClass(QueryResult, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(QueryResult, &SPIRV::iIDRegClass);
SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder);
QueryResultType = GR->getOrCreateSPIRVVectorType(
IntTy, NumActualRetComponents, MIRBuilder);
@@ -1597,7 +1597,7 @@ static bool generateImageSizeQueryInst(const SPIRV::IncomingCall *Call,
bool IsDimBuf = ImgType->getOperand(2).getImm() == SPIRV::Dim::DIM_Buffer;
unsigned Opcode =
IsDimBuf ? SPIRV::OpImageQuerySize : SPIRV::OpImageQuerySizeLod;
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
auto MIB = MIRBuilder.buildInstr(Opcode)
.addDef(QueryResult)
.addUse(GR->getSPIRVTypeID(QueryResultType))
@@ -1653,7 +1653,7 @@ static bool generateImageMiscQueryInst(const SPIRV::IncomingCall *Call,
SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
Register Image = Call->Arguments[0];
- MIRBuilder.getMRI()->setRegClass(Image, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Image, &SPIRV::iIDRegClass);
SPIRV::Dim::Dim ImageDimensionality = static_cast<SPIRV::Dim::Dim>(
GR->getSPIRVTypeForVReg(Image)->getOperand(2).getImm());
(void)ImageDimensionality;
@@ -1717,12 +1717,12 @@ static bool generateReadImageInst(const StringRef DemangledCall,
SPIRVGlobalRegistry *GR) {
Register Image = Call->Arguments[0];
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- MRI->setRegClass(Image, &SPIRV::IDRegClass);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MRI->setRegClass(Image, &SPIRV::iIDRegClass);
+ MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
bool HasOclSampler = DemangledCall.contains_insensitive("ocl_sampler");
bool HasMsaa = DemangledCall.contains_insensitive("msaa");
if (HasOclSampler || HasMsaa)
- MRI->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[2], &SPIRV::iIDRegClass);
if (HasOclSampler) {
Register Sampler = Call->Arguments[1];
@@ -1738,7 +1738,7 @@ static bool generateReadImageInst(const StringRef DemangledCall,
SPIRVType *ImageType = GR->getSPIRVTypeForVReg(Image);
SPIRVType *SampledImageType =
GR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder);
- Register SampledImage = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register SampledImage = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpSampledImage)
.addDef(SampledImage)
@@ -1757,7 +1757,7 @@ static bool generateReadImageInst(const StringRef DemangledCall,
}
LLT LLType = LLT::scalar(GR->getScalarOrVectorBitWidth(TempType));
Register TempRegister = MRI->createGenericVirtualRegister(LLType);
- MRI->setRegClass(TempRegister, &SPIRV::IDRegClass);
+ MRI->setRegClass(TempRegister, &SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(TempType, TempRegister, MIRBuilder.getMF());
MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod)
@@ -1795,9 +1795,9 @@ static bool generateReadImageInst(const StringRef DemangledCall,
static bool generateWriteImageInst(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpImageWrite)
.addUse(Call->Arguments[0]) // Image.
.addUse(Call->Arguments[1]) // Coordinate.
@@ -1828,7 +1828,7 @@ static bool generateSampleImageInst(const StringRef DemangledCall,
Register SampledImage =
Call->ReturnRegister.isValid()
? Call->ReturnRegister
- : MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ : MRI->createVirtualRegister(&SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpSampledImage)
.addDef(SampledImage)
.addUse(GR->getSPIRVTypeID(SampledImageType))
@@ -1852,9 +1852,9 @@ static bool generateSampleImageInst(const StringRef DemangledCall,
"Unable to recognize SPIRV type name: " + ReturnType;
report_fatal_error(DiagMsg.c_str());
}
- MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
- MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
+ MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
+ MRI->setRegClass(Call->Arguments[3], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod)
.addDef(Call->ReturnRegister)
@@ -1974,28 +1974,28 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
SPIRVType *PtrType = GR->getSPIRVTypeForVReg(Call->Arguments[0]);
assert(PtrType->getOpcode() == SPIRV::OpTypePointer &&
PtrType->getOperand(2).isReg());
Register TypeReg = PtrType->getOperand(2).getReg();
SPIRVType *StructType = GR->getSPIRVTypeForVReg(TypeReg);
MachineFunction &MF = MIRBuilder.getMF();
- Register TmpReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register TmpReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(StructType, TmpReg, MF);
// Skip the first arg, it's the destination pointer. OpBuildNDRange takes
// three other arguments, so pass zero constant on absence.
unsigned NumArgs = Call->Arguments.size();
assert(NumArgs >= 2);
Register GlobalWorkSize = Call->Arguments[NumArgs < 4 ? 1 : 2];
- MRI->setRegClass(GlobalWorkSize, &SPIRV::IDRegClass);
+ MRI->setRegClass(GlobalWorkSize, &SPIRV::iIDRegClass);
Register LocalWorkSize =
NumArgs == 2 ? Register(0) : Call->Arguments[NumArgs < 4 ? 2 : 3];
if (LocalWorkSize.isValid())
- MRI->setRegClass(LocalWorkSize, &SPIRV::IDRegClass);
+ MRI->setRegClass(LocalWorkSize, &SPIRV::iIDRegClass);
Register GlobalWorkOffset = NumArgs <= 3 ? Register(0) : Call->Arguments[1];
if (GlobalWorkOffset.isValid())
- MRI->setRegClass(GlobalWorkOffset, &SPIRV::IDRegClass);
+ MRI->setRegClass(GlobalWorkOffset, &SPIRV::iIDRegClass);
if (NumArgs < 4) {
Register Const;
SPIRVType *SpvTy = GR->getSPIRVTypeForVReg(GlobalWorkSize);
@@ -2005,14 +2005,14 @@ static bool buildNDRange(const SPIRV::IncomingCall *Call,
DefInstr->getOperand(3).isReg());
Register GWSPtr = DefInstr->getOperand(3).getReg();
if (!MRI->getRegClassOrNull(GWSPtr))
- MRI->setRegClass(GWSPtr, &SPIRV::IDRegClass);
+ MRI->setRegClass(GWSPtr, &SPIRV::iIDRegClass);
// TODO: Maybe simplify generation of the type of the fields.
unsigned Size = Call->Builtin->Name == "ndrange_3D" ? 3 : 2;
unsigned BitWidth = GR->getPointerSize() == 64 ? 64 : 32;
Type *BaseTy = IntegerType::get(MF.getFunction().getContext(), BitWidth);
Type *FieldTy = ArrayType::get(BaseTy, Size);
SPIRVType *SpvFieldTy = GR->getOrCreateSPIRVType(FieldTy, MIRBuilder);
- GlobalWorkSize = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ GlobalWorkSize = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
GR->assignSPIRVTypeToVReg(SpvFieldTy, GlobalWorkSize, MF);
MIRBuilder.buildInstr(SPIRV::OpLoad)
.addDef(GlobalWorkSize)
@@ -2088,7 +2088,7 @@ static bool buildEnqueueKernel(const SPIRV::IncomingCall *Call,
const SPIRVType *PointerSizeTy = GR->getOrCreateSPIRVPointerType(
Int32Ty, MIRBuilder, SPIRV::StorageClass::Function);
for (unsigned I = 0; I < LocalSizeNum; ++I) {
- Register Reg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register Reg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
MRI->setType(Reg, LLType);
GR->assignSPIRVTypeToVReg(PointerSizeTy, Reg, MIRBuilder.getMF());
auto GEPInst = MIRBuilder.buildIntrinsic(
@@ -2154,7 +2154,7 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call,
switch (Opcode) {
case SPIRV::OpRetainEvent:
case SPIRV::OpReleaseEvent:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode).addUse(Call->Arguments[0]);
case SPIRV::OpCreateUserEvent:
case SPIRV::OpGetDefaultQueue:
@@ -2162,21 +2162,21 @@ static bool generateEnqueueInst(const SPIRV::IncomingCall *Call,
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType));
case SPIRV::OpIsValidEvent:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode)
.addDef(Call->ReturnRegister)
.addUse(GR->getSPIRVTypeID(Call->ReturnType))
.addUse(Call->Arguments[0]);
case SPIRV::OpSetUserEventStatus:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode)
.addUse(Call->Arguments[0])
.addUse(Call->Arguments[1]);
case SPIRV::OpCaptureEventProfilingInfo:
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
- MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
+ MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::iIDRegClass);
return MIRBuilder.buildInstr(Opcode)
.addUse(Call->Arguments[0])
.addUse(Call->Arguments[1])
@@ -2389,21 +2389,21 @@ static bool generateLoadStoreInst(const SPIRV::IncomingCall *Call,
// Add a pointer to the value to load/store.
MIB.addUse(Call->Arguments[0]);
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[0], &SPIRV::iIDRegClass);
// Add a value to store.
if (!IsLoad) {
MIB.addUse(Call->Arguments[1]);
- MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[1], &SPIRV::iIDRegClass);
}
// Add optional memory attributes and an alignment.
unsigned NumArgs = Call->Arguments.size();
if ((IsLoad && NumArgs >= 2) || NumArgs >= 3) {
MIB.addImm(getConstFromIntrinsic(Call->Arguments[IsLoad ? 1 : 2], MRI));
- MRI->setRegClass(Call->Arguments[IsLoad ? 1 : 2], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[IsLoad ? 1 : 2], &SPIRV::iIDRegClass);
}
if ((IsLoad && NumArgs >= 3) || NumArgs >= 4) {
MIB.addImm(getConstFromIntrinsic(Call->Arguments[IsLoad ? 2 : 3], MRI));
- MRI->setRegClass(Call->Arguments[IsLoad ? 2 : 3], &SPIRV::IDRegClass);
+ MRI->setRegClass(Call->Arguments[IsLoad ? 2 : 3], &SPIRV::iIDRegClass);
}
return true;
}
@@ -2496,7 +2496,7 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
if (OrigRetTy && !OrigRetTy->isVoidTy()) {
ReturnType = GR->assignTypeToVReg(OrigRetTy, OrigRet, MIRBuilder);
if (!MIRBuilder.getMRI()->getRegClassOrNull(ReturnRegister))
- MIRBuilder.getMRI()->setRegClass(ReturnRegister, &SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->setRegClass(ReturnRegister, &SPIRV::iIDRegClass);
} else if (OrigRetTy && OrigRetTy->isVoidTy()) {
ReturnRegister = MIRBuilder.getMRI()->createVirtualRegister(&IDRegClass);
MIRBuilder.getMRI()->setType(ReturnRegister, LLT::scalar(32));
diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
index de0b97fbea0c1..316abe866a163 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
@@ -372,7 +372,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
auto MRI = MIRBuilder.getMRI();
Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
- MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(FuncVReg, &SPIRV::iIDRegClass);
if (F.isDeclaration())
GR->add(&F, &MIRBuilder.getMF(), FuncVReg);
FunctionType *FTy = getOriginalFunctionType(F);
@@ -403,7 +403,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
int i = 0;
for (const auto &Arg : F.args()) {
assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
- MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass);
+ MRI->setRegClass(VRegs[i][0], &SPIRV::iIDRegClass);
MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
.addDef(VRegs[i][0])
.addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
@@ -558,7 +558,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
if (MIRBuilder.getDataLayout().getTypeStoreSize(Arg.getType()).isZero())
continue; // Don't handle zero sized types.
Register Reg = MRI->createGenericVirtualRegister(LLT::scalar(32));
- MRI->setRegClass(Reg, &SPIRV::IDRegClass);
+ MRI->setRegClass(Reg, &SPIRV::iIDRegClass);
ToInsert.push_back({Reg});
VRegArgs.push_back(ToInsert.back());
}
@@ -596,7 +596,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// Make sure there's a valid return reg, even for functions returning void.
if (!ResVReg.isValid())
- ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
+ ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
SPIRVType *RetType = GR->assignTypeToVReg(OrigRetTy, ResVReg, MIRBuilder);
// Emit the call instruction and its args.
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index 3ee355a913bf9..6702a0efc638a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -177,7 +177,7 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
// TODO: https://github.com/llvm/llvm-project/issues/88129
LLT LLTy = LLT::scalar(32);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
if (MIRBuilder)
assignTypeToVReg(LLVMIntTy, Res, *MIRBuilder);
else
@@ -311,7 +311,7 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
LLT LLTy = LLT::scalar(EmitIR ? BitWidth : 32);
Res = MF.getRegInfo().createGenericVirtualRegister(LLTy);
- MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ MF.getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignTypeToVReg(LLVMIntTy, Res, MIRBuilder,
SPIRV::AccessQualifier::ReadWrite, EmitIR);
DT.add(ConstInt, &MIRBuilder.getMF(), Res);
@@ -410,7 +410,7 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
LLT LLTy = LLT::scalar(32);
Register SpvVecConst =
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, SpvVecConst, *CurMF);
DT.add(CA, CurMF, SpvVecConst);
MachineInstrBuilder MIB;
@@ -512,7 +512,7 @@ Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull(
LLT LLTy = EmitIR ? LLT::fixed_vector(ElemCnt, BitWidth) : LLT::scalar(32);
Register SpvVecConst =
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, SpvVecConst, *CurMF);
DT.add(CA, CurMF, SpvVecConst);
if (EmitIR) {
@@ -564,7 +564,7 @@ SPIRVGlobalRegistry::getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder,
if (!Res.isValid()) {
LLT LLTy = LLT::pointer(LLVMPtrTy->getAddressSpace(), PointerSize);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
MIRBuilder.buildInstr(SPIRV::OpConstantNull)
.addDef(Res)
@@ -587,7 +587,7 @@ Register SPIRVGlobalRegistry::buildConstantSampler(
auto Sampler =
ResReg.isValid()
? ResReg
- : MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
+ : MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
auto Res = MIRBuilder.buildInstr(SPIRV::OpConstantSampler)
.addDef(Sampler)
.addUse(getSPIRVTypeID(SampTy))
@@ -1438,7 +1438,7 @@ Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I,
return Res;
LLT LLTy = LLT::scalar(32);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
DT.add(UV, CurMF, Res);
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index ae4e039744286..a90f57ac8f824 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -96,10 +96,10 @@ SPIRVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
: &SPIRV::fIDRegClass);
else if (VT.isInteger())
RC = VT.isVector() ? &SPIRV::vIDRegClass
- : (VT.getScalarSizeInBits() > 32 ? &SPIRV::ID64RegClass
- : &SPIRV::IDRegClass);
+ : (VT.getScalarSizeInBits() > 32 ? &SPIRV::iID64RegClass
+ : &SPIRV::iIDRegClass);
else
- RC = &SPIRV::IDRegClass;
+ RC = &SPIRV::iIDRegClass;
return std::make_pair(0u, RC);
}
@@ -125,7 +125,7 @@ static void doInsertBitcast(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI,
*STI.getRegBankInfo());
if (!Res)
report_fatal_error("insert validation bitcast: cannot constrain all uses");
- MRI->setRegClass(NewReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(NewReg, &SPIRV::iIDRegClass);
GR.assignSPIRVTypeToVReg(NewPtrType, NewReg, MIB.getMF());
I.getOperand(OpIdx).setReg(NewReg);
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 9d06711204edc..c4b09dd6bfe43 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -17,8 +17,8 @@ include "SPIRVSymbolicOperands.td"
let isCodeGenOnly=1 in {
def ASSIGN_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
def DECL_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
- def GET_ID: Pseudo<(outs ID:$dst_id), (ins ANYID:$src)>;
- def GET_ID64: Pseudo<(outs ID64:$dst_id), (ins ANYID:$src)>;
+ def GET_ID: Pseudo<(outs iID:$dst_id), (ins ANYID:$src)>;
+ def GET_ID64: Pseudo<(outs iID64:$dst_id), (ins ANYID:$src)>;
def GET_fID: Pseudo<(outs fID:$dst_id), (ins ANYID:$src)>;
def GET_fID64: Pseudo<(outs fID64:$dst_id), (ins ANYID:$src)>;
def GET_pID32: Pseudo<(outs pID32:$dst_id), (ins ANYID:$src)>;
@@ -40,18 +40,18 @@ class BinOp<string name, bits<16> opCode, list<dag> pattern=[]>
"$dst = "#name#" $src_ty $src $src2", pattern>;
class BinOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
- : Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
- "$dst = "#name#" $src_ty $src $src2", [(set ID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
+ : Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
+ "$dst = "#name#" $src_ty $src $src2", [(set iID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
class TernOpTyped<string name, bits<16> opCode, RegisterClass CCond, RegisterClass CID, SDNode node>
- : Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
- "$dst = "#name#" $src_ty $cond $src1 $src2", [(set ID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;
+ : Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
+ "$dst = "#name#" $src_ty $cond $src1 $src2", [(set iID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;
multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0, bit genV = 0> {
if genF then
def S: BinOpTyped<name, opCode, fID, node>;
else
- def S: BinOpTyped<name, opCode, ID, node>;
+ def S: BinOpTyped<name, opCode, iID, node>;
if genV then {
if genF then
def V: BinOpTyped<name, opCode, vfID, node>;
@@ -62,32 +62,32 @@ multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0
multiclass TernOpTypedGen<string name, bits<16> opCode, SDNode node, bit genP = 1, bit genI = 1, bit genF = 0, bit genV = 0> {
if genF then {
- def SFSCond: TernOpTyped<name, opCode, ID, fID, node>;
+ def SFSCond: TernOpTyped<name, opCode, iID, fID, node>;
def SFVCond: TernOpTyped<name, opCode, vID, fID, node>;
}
if genI then {
- def SISCond: TernOpTyped<name, opCode, ID, ID, node>;
- def SIVCond: TernOpTyped<name, opCode, vID, ID, node>;
+ def SISCond: TernOpTyped<name, opCode, iID, iID, node>;
+ def SIVCond: TernOpTyped<name, opCode, vID, iID, node>;
}
if genP then {
- def SPSCond32: TernOpTyped<name, opCode, ID, pID32, node>;
+ def SPSCond32: TernOpTyped<name, opCode, iID, pID32, node>;
def SPVCond32: TernOpTyped<name, opCode, vID, pID32, node>;
- def SPSCond64: TernOpTyped<name, opCode, ID, pID64, node>;
+ def SPSCond64: TernOpTyped<name, opCode, iID, pID64, node>;
def SPVCond64: TernOpTyped<name, opCode, vID, pID64, node>;
}
if genV then {
if genF then {
- def VFSCond: TernOpTyped<name, opCode, ID, vfID, node>;
+ def VFSCond: TernOpTyped<name, opCode, iID, vfID, node>;
def VFVCond: TernOpTyped<name, opCode, vID, vfID, node>;
}
if genI then {
- def VISCond: TernOpTyped<name, opCode, ID, vID, node>;
+ def VISCond: TernOpTyped<name, opCode, iID, vID, node>;
def VIVCond: TernOpTyped<name, opCode, vID, vID, node>;
}
if genP then {
- def VPSCond32: TernOpTyped<name, opCode, ID, vpID32, node>;
+ def VPSCond32: TernOpTyped<name, opCode, iID, vpID32, node>;
def VPVCond32: TernOpTyped<name, opCode, vID, vpID32, node>;
- def VPSCond64: TernOpTyped<name, opCode, ID, vpID64, node>;
+ def VPSCond64: TernOpTyped<name, opCode, iID, vpID64, node>;
def VPVCond64: TernOpTyped<name, opCode, vID, vpID64, node>;
}
}
@@ -97,8 +97,8 @@ class UnOp<string name, bits<16> opCode, list<dag> pattern=[]>
: Op<opCode, (outs ANYID:$dst), (ins TYPE:$type, ANYID:$src),
"$dst = "#name#" $type $src", pattern>;
class UnOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
- : Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CID:$src),
- "$dst = "#name#" $src_ty $src", [(set ID:$dst, (assigntype (node CID:$src), TYPE:$src_ty))]>;
+ : Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src),
+ "$dst = "#name#" $src_ty $src", [(set iID:$dst, (assigntype (node CID:$src), TYPE:$src_ty))]>;
class SimpleOp<string name, bits<16> opCode>: Op<opCode, (outs), (ins), name>;
@@ -240,16 +240,16 @@ def ConstPseudoFalse: IntImmLeaf<i32, [{ return Imm.getBitWidth() == 1 && Imm.ge
def ConstPseudoNull: IntImmLeaf<i64, [{ return Imm.isZero(); }]>;
multiclass IntFPImm<bits<16> opCode, string name> {
- def I: Op<opCode, (outs ID:$dst), (ins TYPE:$type, ID:$src, variable_ops),
- "$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
+ def I: Op<opCode, (outs iID:$dst), (ins TYPE:$type, iID:$src, variable_ops),
+ "$dst = "#name#" $type", [(set iID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
def F: Op<opCode, (outs fID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
"$dst = "#name#" $type", [(set fID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
}
-def OpConstantTrue: Op<41, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
- [(set ID:$dst, (assigntype ConstPseudoTrue, TYPE:$src_ty))]>;
-def OpConstantFalse: Op<42, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantFalse $src_ty",
- [(set ID:$dst, (assigntype ConstPseudoFalse, TYPE:$src_ty))]>;
+def OpConstantTrue: Op<41, (outs iID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
+ [(set iID:$dst, (assigntype ConstPseudoTrue, TYPE:$src_ty))]>;
+def OpConstantFalse: Op<42, (outs iID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantFalse $src_ty",
+ [(set iID:$dst, (assigntype ConstPseudoFalse, TYPE:$src_ty))]>;
defm OpConstant: IntFPImm<43, "OpConstant">;
@@ -468,8 +468,10 @@ def OpConvertBF16ToFINTEL : UnOp<"OpConvertBF16ToFINTEL", 6117>;
// 3.42.12 Composite Instructions
+//def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
+// "$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
- "$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
+ "$res = OpVectorExtractDynamic $type $vec $idx">;
def OpVectorInsertDynamic: Op<78, (outs ID:$res), (ins TYPE:$ty, ID:$vec, ID:$comp, ID:$idx),
"$res = OpVectorInsertDynamic $ty $vec $comp $idx">;
@@ -520,8 +522,8 @@ def OpMatrixTimesMatrix: BinOp<"OpMatrixTimesMatrix", 146>;
def OpOuterProduct: BinOp<"OpOuterProduct", 147>;
def OpDot: BinOp<"OpDot", 148>;
-def OpIAddCarry: BinOpTyped<"OpIAddCarry", 149, ID, addc>;
-def OpISubBorrow: BinOpTyped<"OpISubBorrow", 150, ID, subc>;
+def OpIAddCarry: BinOpTyped<"OpIAddCarry", 149, iID, addc>;
+def OpISubBorrow: BinOpTyped<"OpISubBorrow", 150, iID, subc>;
def OpUMulExtended: BinOp<"OpUMulExtended", 151>;
def OpSMulExtended: BinOp<"OpSMulExtended", 152>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 84c8491c6b7c8..9b6cb176ae65d 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -348,7 +348,7 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
if (Res)
return Res;
}
- MRI->setRegClass(DstReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(DstReg, &SPIRV::iIDRegClass);
MRI->replaceRegWith(SrcReg, DstReg);
I.removeFromParent();
return true;
@@ -950,7 +950,7 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg,
Register ValueReg = I.getOperand(2).getReg();
if (NegateOpcode != 0) {
// Translation with negative value operand is requested
- Register TmpReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register TmpReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
Result |= selectUnOpWithSrc(TmpReg, ResType, I, ValueReg, NegateOpcode);
ValueReg = TmpReg;
}
@@ -986,7 +986,7 @@ bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const {
if (!ResType) {
// There was no "assign type" actions, let's fix this now
ResType = ScalarType;
- MRI->setRegClass(ResVReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(ResVReg, &SPIRV::iIDRegClass);
MRI->setType(ResVReg, LLT::scalar(GR.getScalarOrVectorBitWidth(ResType)));
GR.assignSPIRVTypeToVReg(ResType, ResVReg, *GR.CurMF);
}
@@ -1047,7 +1047,7 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,
Register Cmp = I.getOperand(3).getReg();
Register Val = I.getOperand(4).getReg();
SPIRVType *SpvValTy = GR.getSPIRVTypeForVReg(Val);
- Register ACmpRes = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register ACmpRes = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
const DebugLoc &DL = I.getDebugLoc();
bool Result =
BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpAtomicCompareExchange))
@@ -1060,7 +1060,7 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,
.addUse(Val)
.addUse(Cmp)
.constrainAllUses(TII, TRI, RBI);
- Register CmpSuccReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register CmpSuccReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
SPIRVType *BoolTy = GR.getOrCreateSPIRVBoolType(I, TII);
Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpIEqual))
.addDef(CmpSuccReg)
@@ -1068,7 +1068,7 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,
.addUse(ACmpRes)
.addUse(Cmp)
.constrainAllUses(TII, TRI, RBI);
- Register TmpReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register TmpReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert))
.addDef(TmpReg)
.addUse(GR.getSPIRVTypeID(ResType))
@@ -1157,7 +1157,7 @@ bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg,
return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr);
// Casting between 2 eligible pointers using Generic as an intermediary.
if (isGenericCastablePtr(SrcSC) && isGenericCastablePtr(DstSC)) {
- Register Tmp = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register Tmp = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
SPIRVType *GenericPtrTy = GR.getOrCreateSPIRVPointerType(
GR.getPointeeType(SrcPtrTy), I, TII, SPIRV::StorageClass::Generic);
MachineBasicBlock &BB = *I.getParent();
@@ -1312,7 +1312,7 @@ bool SPIRVInstructionSelector::selectAnyOrAll(Register ResVReg,
if (IsVectorTy) {
NotEqualReg = IsBoolTy ? InputRegister
- : MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ : MRI->createVirtualRegister(&SPIRV::iIDRegClass);
const unsigned NumElts = InputType->getOperand(2).getImm();
SpvBoolTy = GR.getOrCreateSPIRVVectorType(SpvBoolTy, NumElts, I, TII);
}
@@ -1748,7 +1748,7 @@ bool SPIRVInstructionSelector::selectIToF(Register ResVReg,
const unsigned NumElts = ResType->getOperand(2).getImm();
TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII);
}
- SrcReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ SrcReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
selectSelect(SrcReg, TmpType, I, false);
}
return selectUnOpWithSrc(ResVReg, ResType, I, SrcReg, Opcode);
@@ -1779,7 +1779,7 @@ bool SPIRVInstructionSelector::selectIntToBool(Register IntReg,
const SPIRVType *IntTy,
const SPIRVType *BoolTy) const {
// To truncate to a bool, we use OpBitwiseAnd 1 and OpINotEqual to zero.
- Register BitIntReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register BitIntReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
bool IsVectorTy = IntTy->getOpcode() == SPIRV::OpTypeVector;
unsigned Opcode = IsVectorTy ? SPIRV::OpBitwiseAndV : SPIRV::OpBitwiseAndS;
Register Zero = buildZerosVal(IntTy, I);
@@ -1990,7 +1990,7 @@ bool SPIRVInstructionSelector::wrapIntoSpecConstantOp(
continue;
}
// Create a new register for the wrapper
- WrapReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ WrapReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
GR.add(OpDefine, MF, WrapReg);
CompositeArgs.push_back(WrapReg);
// Decorate the wrapper register and generate a new instruction
@@ -2304,7 +2304,7 @@ bool SPIRVInstructionSelector::selectGlobalValue(
// module analysis stage.
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
- MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass);
+ MRI->setRegClass(FuncVReg, &SPIRV::iIDRegClass);
MachineInstrBuilder MB =
BuildMI(BB, I, I.getDebugLoc(),
TII.get(SPIRV::OpConstantFunctionPointerINTEL))
@@ -2371,7 +2371,7 @@ bool SPIRVInstructionSelector::selectLog10(Register ResVReg,
MachineBasicBlock &BB = *I.getParent();
// Build log2(x).
- Register VarReg = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register VarReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
bool Result =
BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
.addDef(VarReg)
@@ -2422,7 +2422,7 @@ bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
// Create new register for GlobalInvocationID builtin variable.
Register NewRegister =
- MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
+ MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
MIRBuilder.getMRI()->setType(NewRegister, LLT::pointer(0, 32));
GR.assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF());
@@ -2435,7 +2435,7 @@ bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
// Create new register for loading value.
MachineRegisterInfo *MRI = MIRBuilder.getMRI();
- Register LoadedRegister = MRI->createVirtualRegister(&SPIRV::IDRegClass);
+ Register LoadedRegister = MRI->createVirtualRegister(&SPIRV::iIDRegClass);
MIRBuilder.getMRI()->setType(LoadedRegister, LLT::pointer(0, 32));
GR.assignSPIRVTypeToVReg(Vec3Ty, LoadedRegister, MIRBuilder.getMF());
diff --git a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
index c3842f0266706..44685be3d68ad 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPostLegalizer.cpp
@@ -102,7 +102,7 @@ static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
if (!ResType) {
// There was no "assign type" actions, let's fix this now
ResType = ScalarType;
- MRI.setRegClass(ResVReg, &SPIRV::IDRegClass);
+ MRI.setRegClass(ResVReg, &SPIRV::iIDRegClass);
MRI.setType(ResVReg,
LLT::scalar(GR->getScalarOrVectorBitWidth(ResType)));
GR->assignSPIRVTypeToVReg(ResType, ResVReg, *GR->CurMF);
@@ -124,7 +124,7 @@ static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
if (!ResVType)
continue;
// Set type & class
- MRI.setRegClass(ResVReg, &SPIRV::IDRegClass);
+ MRI.setRegClass(ResVReg, &SPIRV::iIDRegClass);
MRI.setType(ResVReg,
LLT::scalar(GR->getScalarOrVectorBitWidth(ResVType)));
GR->assignSPIRVTypeToVReg(ResVType, ResVReg, *GR->CurMF);
@@ -139,7 +139,7 @@ static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
// Restore usual instructions pattern for the newly inserted
// instruction
MRI.setRegClass(ResVReg, MRI.getType(ResVReg).isVector()
- ? &SPIRV::IDRegClass
+ ? &SPIRV::iIDRegClass
: &SPIRV::ANYIDRegClass);
MRI.setType(ResVReg, LLT::scalar(32));
insertAssignInstr(ResVReg, nullptr, ResVType, GR, MIB, MRI);
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 3ff0a8e1125ad..6838f4bf9410f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -287,7 +287,7 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
if (SpvType)
GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
if (!MRI.getRegClassOrNull(Reg))
- MRI.setRegClass(Reg, &SPIRV::IDRegClass);
+ MRI.setRegClass(Reg, &SPIRV::iIDRegClass);
}
}
return SpvType;
@@ -337,7 +337,7 @@ static const TargetRegisterClass *getRegClass(SPIRVType *SpvType,
return &SPIRV::vIDRegClass;
}
}
- return &SPIRV::IDRegClass;
+ return &SPIRV::iIDRegClass;
}
static std::pair<Register, unsigned>
@@ -631,7 +631,7 @@ insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
if (!AsmTargetReg.isValid()) {
// define vendor specific assembly target or dialect
AsmTargetReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
- MRI.setRegClass(AsmTargetReg, &SPIRV::IDRegClass);
+ MRI.setRegClass(AsmTargetReg, &SPIRV::iIDRegClass);
auto AsmTargetMIB =
MIRBuilder.buildInstr(SPIRV::OpAsmTargetINTEL).addDef(AsmTargetReg);
addStringImm(ST.getTargetTripleAsStr(), AsmTargetMIB);
@@ -651,7 +651,7 @@ insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
// define vendor specific assembly instructions string
Register AsmReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
- MRI.setRegClass(AsmReg, &SPIRV::IDRegClass);
+ MRI.setRegClass(AsmReg, &SPIRV::iIDRegClass);
auto AsmMIB = MIRBuilder.buildInstr(SPIRV::OpAsmINTEL)
.addDef(AsmReg)
.addUse(GR->getSPIRVTypeID(RetType))
@@ -694,7 +694,7 @@ insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
}
if (!DefReg.isValid()) {
DefReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
- MRI.setRegClass(DefReg, &SPIRV::IDRegClass);
+ MRI.setRegClass(DefReg, &SPIRV::iIDRegClass);
SPIRVType *VoidType = GR->getOrCreateSPIRVType(
Type::getVoidTy(MF.getFunction().getContext()), MIRBuilder);
GR->assignSPIRVTypeToVReg(VoidType, DefReg, MF);
diff --git a/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td b/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
index e81d969564046..52286c4f5cc11 100644
--- a/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
+++ b/llvm/lib/Target/SPIRV/SPIRVRegisterBanks.td
@@ -10,4 +10,4 @@
// as InstructionSelector RegClass checking code relies on them
def TYPERegBank : RegisterBank<"TYPEBank", [TYPE]>;
-def IDRegBank : RegisterBank<"IDBank", [ID, ID64, fID, fID64, pID32, pID64, vID, vfID, vpID32, vpID64]>;
+def IDRegBank : RegisterBank<"IDBank", [ID]>;
diff --git a/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td b/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
index 17f6ba59cc5de..936ad8e684b3e 100644
--- a/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVRegisterInfo.td
@@ -39,8 +39,8 @@ let Namespace = "SPIRV" in {
def vpID320 : Register<"vpID320">;
def vpID640 : Register<"vpID640">;
- def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
- def ID64 : RegisterClass<"SPIRV", [i64], 32, (add ID640)>;
+ def iID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
+ def iID64 : RegisterClass<"SPIRV", [i64], 32, (add ID640)>;
def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>;
def fID64 : RegisterClass<"SPIRV", [f64], 32, (add fID640)>;
def pID32 : RegisterClass<"SPIRV", [p32], 32, (add pID320)>;
@@ -50,6 +50,12 @@ let Namespace = "SPIRV" in {
def vpID32 : RegisterClass<"SPIRV", [v2p32], 32, (add vpID320)>;
def vpID64 : RegisterClass<"SPIRV", [v2p64], 32, (add vpID640)>;
+ def ID : RegisterClass<
+ "SPIRV",
+ [i32, i64, f32, f64, p32, p64, v2i32, v2f32, v2p32, v2p64],
+ 32,
+ (add iID, iID64, fID, fID64, pID32, pID64, vID, vfID, vpID32, vpID64)>;
+
def ANYID : RegisterClass<
"SPIRV",
[i32, i64, f32, f64, p32, p64, v2i32, v2f32, v2p32, v2p64],
diff --git a/llvm/test/CodeGen/SPIRV/atomicrmw.ll b/llvm/test/CodeGen/SPIRV/atomicrmw.ll
index 8148477157536..5f95a974ba671 100644
--- a/llvm/test/CodeGen/SPIRV/atomicrmw.ll
+++ b/llvm/test/CodeGen/SPIRV/atomicrmw.ll
@@ -1,4 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[#Int:]] = OpTypeInt 32 0
; CHECK-DAG: %[[#Scope_Device:]] = OpConstant %[[#Int]] 1{{$}}
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