[llvm] [AMDGPU] Set register bank for i1 register copies (PR #96155)

[Jun Wang via llvm-commits]

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@@ -201,3 +203,390 @@ body: |
     %2:vcc(s1) = COPY %1
     S_ENDPGM 0, implicit %2
 ...
+
+---
+name: copy_sgpr_64_to_s1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr4_sgpr5
+    ; CHECK-LABEL: name: copy_sgpr_64_to_s1
+    ; CHECK: liveins: $sgpr4_sgpr5
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5
+    ; CHECK-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[CONST1]], [[CONST2]]
+    ;
+    ; GFX10-LABEL: name: copy_sgpr_64_to_s1
+    ; GFX10: liveins: $sgpr4_sgpr5
+    ; GFX10-NEXT: {{  $}}
+    ; GFX10-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5
+    ; GFX10-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
+    ; GFX10-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
+    ; GFX10-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[CONST1]], [[CONST2]]
+    %0:_(s1) = COPY $sgpr4_sgpr5
+    %1:_(s32) = G_ZEXT %0:_(s1)
+...
+
+---
+name: copy_sgpr_32_to_s1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: copy_sgpr_32_to_s1
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr0
----------------
jwanggit86 wrote:

For wave64, removed the checks involving copy 32b physical reg to vcc.

https://github.com/llvm/llvm-project/pull/96155