[llvm] [SLP] The order of store chains needs to consider the size of the values. (PR #101810)

[via llvm-commits]

https://github.com/tcwzxx updated https://github.com/llvm/llvm-project/pull/101810

>From d134ca855aa76cc8e776142a740973f0a91fcdf5 Mon Sep 17 00:00:00 2001
From: tcwzxx <tcwzxx at gmail.com>
Date: Sat, 3 Aug 2024 21:11:32 +0800
Subject: [PATCH] The order of store chains needs to consider the size of the
 values

---
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp        |  8 ++++++++
 .../Transforms/SLPVectorizer/X86/stores_mix_sizes.ll   | 10 +---------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index ed9dfa66dc0b5..975696dfe3b82 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -19123,6 +19123,14 @@ bool SLPVectorizerPass::vectorizeStoreChains(BoUpSLP &R) {
     if (V->getPointerOperandType()->getTypeID() >
         V2->getPointerOperandType()->getTypeID())
       return false;
+    if (V->getValueOperand()->getType()->getScalarSizeInBits() <
+        V2->getValueOperand()->getType()->getScalarSizeInBits()) {
+      return true;
+    }
+    if (V->getValueOperand()->getType()->getScalarSizeInBits() >
+        V2->getValueOperand()->getType()->getScalarSizeInBits()) {
+      return false;
+    }
     // UndefValues are compatible with all other values.
     if (isa<UndefValue>(V->getValueOperand()) ||
         isa<UndefValue>(V2->getValueOperand()))
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/stores_mix_sizes.ll b/llvm/test/Transforms/SLPVectorizer/X86/stores_mix_sizes.ll
index 1e2a87b12807c..3795b0e7b399b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/stores_mix_sizes.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/stores_mix_sizes.ll
@@ -5,17 +5,9 @@ define void @test(ptr %p) {
 ; CHECK-SAME: ptr [[P:%.*]]) {
 ; CHECK-NEXT:  [[ENTRY:.*:]]
 ; CHECK-NEXT:    [[IDX1:%.*]] = getelementptr i8, ptr [[P]], i64 1
-; CHECK-NEXT:    store i8 0, ptr [[IDX1]], align 4
 ; CHECK-NEXT:    [[IDX_64_9:%.*]] = getelementptr i64, ptr [[P]], i64 9
 ; CHECK-NEXT:    store i64 1, ptr [[IDX_64_9]], align 8
-; CHECK-NEXT:    [[IDX2:%.*]] = getelementptr i8, ptr [[P]], i64 2
-; CHECK-NEXT:    store <4 x i8> zeroinitializer, ptr [[IDX2]], align 4
-; CHECK-NEXT:    [[IDX6:%.*]] = getelementptr i8, ptr [[P]], i64 6
-; CHECK-NEXT:    store i8 0, ptr [[IDX6]], align 4
-; CHECK-NEXT:    [[IDX7:%.*]] = getelementptr i8, ptr [[P]], i64 7
-; CHECK-NEXT:    store i8 0, ptr [[IDX7]], align 4
-; CHECK-NEXT:    [[IDX8:%.*]] = getelementptr i8, ptr [[P]], i64 8
-; CHECK-NEXT:    store i8 0, ptr [[IDX8]], align 4
+; CHECK-NEXT:    store <8 x i8> zeroinitializer, ptr [[IDX1]], align 4
 ; CHECK-NEXT:    ret void
 ;
   entry: