[llvm] [SPIR-V] Improve test suite pass rate when expensive checks are on (PR #101732)
Vyacheslav Levytskyy via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 5 09:44:30 PDT 2024
https://github.com/VyacheslavLevytskyy updated https://github.com/llvm/llvm-project/pull/101732
>From 8f1974faee06eee5cb8707379725c0f285df87ed Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Fri, 2 Aug 2024 11:35:25 -0700
Subject: [PATCH 1/3] scalar virtual registers have proper bit width
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 28 ++++++++++++++++
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 5 ++-
llvm/test/CodeGen/SPIRV/empty.ll | 5 ++-
llvm/test/CodeGen/SPIRV/transcoding/fadd.ll | 33 +++++++++++++++++--
llvm/test/CodeGen/SPIRV/transcoding/non32.ll | 2 +-
llvm/test/CodeGen/SPIRV/types/or-i1.ll | 2 +-
llvm/test/CodeGen/SPIRV/unnamed-global.ll | 7 ++--
7 files changed, 73 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index ed786bd33aa05..262776deaa049 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -76,6 +76,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
SPIRVGlobalRegistry &GR;
MachineRegisterInfo *MRI;
SyncScopeIDs SSIDs;
+ MachineFunction *HasVRegsReset = nullptr;
/// We need to keep track of the number we give to anonymous global values to
/// generate the same name every time when this is needed.
@@ -101,6 +102,8 @@ class SPIRVInstructionSelector : public InstructionSelector {
#undef GET_GLOBALISEL_TEMPORARIES_DECL
private:
+ void resetVRegsType(MachineFunction &MF);
+
// tblgen-erated 'select' implementation, used as the initial selector for
// the patterns that don't require complex C++.
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
@@ -285,12 +288,37 @@ void SPIRVInstructionSelector::setupMF(MachineFunction &MF, GISelKnownBits *KB,
InstructionSelector::setupMF(MF, KB, CoverageInfo, PSI, BFI);
}
+// To ensure that pattern matching rules are working.
+void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
+ if (HasVRegsReset == &MF)
+ return;
+ HasVRegsReset = &MF;
+
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
+ LLT Ty = MRI.getType(Reg);
+ if (Ty.isScalar()) {
+ unsigned Bits = Ty.getScalarSizeInBits();
+ switch (Bits) {
+ //case 1:
+ case 32:
+ break;
+ default:
+ MRI.setType(Reg, LLT::scalar(32));
+ }
+ }
+ }
+}
+
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI);
// Defined in SPIRVLegalizerInfo.cpp.
extern bool isTypeFoldingSupported(unsigned Opcode);
bool SPIRVInstructionSelector::select(MachineInstr &I) {
+ resetVRegsType(*I.getParent()->getParent());
+
assert(I.getParent() && "Instruction should be in a basic block!");
assert(I.getParent()->getParent() && "Instruction should be in a function!");
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 099557a608185..67ef4fb124125 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -315,7 +315,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
SpvType = GR.getSPIRVTypeForVReg(SrcReg);
assert(SpvType && "VReg is expected to have SPIRV type");
LLT SrcLLT = MRI.getType(SrcReg);
- LLT NewT = LLT::scalar(32);
+ LLT NewT;
bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
bool IsVectorFloat =
SpvType->getOpcode() == SPIRV::OpTypeVector &&
@@ -348,6 +348,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
}
}
} else if (SrcLLT.isVector()) {
+ NewT = LLT::scalar(32); //LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
NewT = LLT::fixed_vector(2, NewT);
if (IsFloat) {
GetIdOp = SPIRV::GET_vfID;
@@ -356,6 +357,8 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
GetIdOp = SPIRV::GET_vID;
DstClass = &SPIRV::vIDRegClass;
}
+ } else {
+ NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
}
Register IdReg = MRI.createGenericVirtualRegister(NewT);
MRI.setRegClass(IdReg, DstClass);
diff --git a/llvm/test/CodeGen/SPIRV/empty.ll b/llvm/test/CodeGen/SPIRV/empty.ll
index 390ab329aea33..29af913a0daee 100644
--- a/llvm/test/CodeGen/SPIRV/empty.ll
+++ b/llvm/test/CodeGen/SPIRV/empty.ll
@@ -1,4 +1,7 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: OpCapability Addresses
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll b/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
index af76c0e96f9f4..d84fd492a86a8 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/fadd.ll
@@ -8,6 +8,13 @@
; CHECK-SPIRV: OpName %[[#r5:]] "r5"
; CHECK-SPIRV: OpName %[[#r6:]] "r6"
; CHECK-SPIRV: OpName %[[#r7:]] "r7"
+; CHECK-SPIRV: OpName %[[#r1d:]] "r1"
+; CHECK-SPIRV: OpName %[[#r2d:]] "r2"
+; CHECK-SPIRV: OpName %[[#r3d:]] "r3"
+; CHECK-SPIRV: OpName %[[#r4d:]] "r4"
+; CHECK-SPIRV: OpName %[[#r5d:]] "r5"
+; CHECK-SPIRV: OpName %[[#r6d:]] "r6"
+; CHECK-SPIRV: OpName %[[#r7d:]] "r7"
; CHECK-SPIRV-NOT: OpDecorate %[[#r1]] FPFastMathMode
; CHECK-SPIRV-DAG: OpDecorate %[[#r2]] FPFastMathMode NotNaN
; CHECK-SPIRV-DAG: OpDecorate %[[#r3]] FPFastMathMode NotInf
@@ -15,7 +22,9 @@
; CHECK-SPIRV-DAG: OpDecorate %[[#r5]] FPFastMathMode AllowRecip
; CHECK-SPIRV-DAG: OpDecorate %[[#r6]] FPFastMathMode NotNaN|NotInf|NSZ|AllowRecip|Fast
; CHECK-SPIRV-DAG: OpDecorate %[[#r7]] FPFastMathMode NotNaN|NotInf
-; CHECK-SPIRV: %[[#float:]] = OpTypeFloat 32
+; CHECK-SPIRV-DAG: %[[#float:]] = OpTypeFloat 32
+; CHECK-SPIRV-DAG: %[[#double:]] = OpTypeFloat 64
+
; CHECK-SPIRV: %[[#r1]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r2]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r3]] = OpFAdd %[[#float]]
@@ -23,8 +32,7 @@
; CHECK-SPIRV: %[[#r5]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r6]] = OpFAdd %[[#float]]
; CHECK-SPIRV: %[[#r7]] = OpFAdd %[[#float]]
-
-define spir_kernel void @testFAdd(float %a, float %b) {
+define spir_kernel void @testFAdd_float(float %a, float %b) {
entry:
%r1 = fadd float %a, %b
%r2 = fadd nnan float %a, %b
@@ -35,3 +43,22 @@ entry:
%r7 = fadd nnan ninf float %a, %b
ret void
}
+
+; CHECK-SPIRV: %[[#r1d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r2d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r3d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r4d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r5d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r6d]] = OpFAdd %[[#double]]
+; CHECK-SPIRV: %[[#r7d]] = OpFAdd %[[#double]]
+define spir_kernel void @testFAdd_double(double %a, double %b) {
+entry:
+ %r1 = fadd double %a, %b
+ %r2 = fadd nnan double %a, %b
+ %r3 = fadd ninf double %a, %b
+ %r4 = fadd nsz double %a, %b
+ %r5 = fadd arcp double %a, %b
+ %r6 = fadd fast double %a, %b
+ %r7 = fadd nnan ninf double %a, %b
+ ret void
+}
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
index d44e32141db75..f3f73ce4fee76 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/non32.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
; CHECK: OpTypeInt 16
; CHECK: OpIAdd
diff --git a/llvm/test/CodeGen/SPIRV/types/or-i1.ll b/llvm/test/CodeGen/SPIRV/types/or-i1.ll
index 32dc258d85554..3dda3ff8c3c66 100644
--- a/llvm/test/CodeGen/SPIRV/types/or-i1.ll
+++ b/llvm/test/CodeGen/SPIRV/types/or-i1.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK-DAG: %[[#BOOL:]] = OpTypeBool
diff --git a/llvm/test/CodeGen/SPIRV/unnamed-global.ll b/llvm/test/CodeGen/SPIRV/unnamed-global.ll
index d2cd4ea8cafc3..f72334bd7752e 100644
--- a/llvm/test/CodeGen/SPIRV/unnamed-global.ll
+++ b/llvm/test/CodeGen/SPIRV/unnamed-global.ll
@@ -1,5 +1,8 @@
-; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
-; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
; CHECK: %[[TyInt:.*]] = OpTypeInt 8 0
; CHECK: %[[ConstInt:.*]] = OpConstant %[[TyInt]] 123
>From 467b6df4ae1986164e0dd2620ed59c5a1bffef1e Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Fri, 2 Aug 2024 12:32:00 -0700
Subject: [PATCH 2/3] improve virtual registers of vector type
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 4 +++
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 27 ++++++++++++-------
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 262776deaa049..6cb68c98ec3aa 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -307,6 +307,10 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
default:
MRI.setType(Reg, LLT::scalar(32));
}
+ } else if (!Ty.isPointer()) {
+ if (auto *Def = MRI.getVRegDef(Reg))
+ if (Def->getOpcode() == SPIRV::ASSIGN_TYPE)
+ MRI.setType(Reg, LLT::scalar(32));
}
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 67ef4fb124125..6323fcfbe8051 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -308,6 +308,14 @@ static void widenScalarLLTNextPow2(Register Reg, MachineRegisterInfo &MRI) {
MRI.setType(Reg, LLT::scalar(NewSz));
}
+inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
+ bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
+ return IsFloat ? true
+ : SpvType->getOpcode() == SPIRV::OpTypeVector &&
+ GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())
+ ->getOpcode() == SPIRV::OpTypeFloat;
+}
+
static std::pair<Register, unsigned>
createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
const SPIRVGlobalRegistry &GR) {
@@ -316,12 +324,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
assert(SpvType && "VReg is expected to have SPIRV type");
LLT SrcLLT = MRI.getType(SrcReg);
LLT NewT;
- bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
- bool IsVectorFloat =
- SpvType->getOpcode() == SPIRV::OpTypeVector &&
- GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())->getOpcode() ==
- SPIRV::OpTypeFloat;
- IsFloat |= IsVectorFloat;
+ bool IsFloat = getIsFloat(SpvType, GR);
auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
auto DstClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
if (SrcLLT.isPointer()) {
@@ -384,8 +387,10 @@ Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy,
if (auto *RC = MRI.getRegClassOrNull(Reg)) {
MRI.setRegClass(NewReg, RC);
} else {
- MRI.setRegClass(NewReg, &SPIRV::IDRegClass);
- MRI.setRegClass(Reg, &SPIRV::IDRegClass);
+ bool IsFloat = false;//getIsFloat(SpirvTy, *GR);
+ auto RegClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
+ MRI.setRegClass(NewReg, RegClass);
+ MRI.setRegClass(Reg, RegClass);
}
GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
// This is to make it convenient for Legalizer to get the SPIRVType
@@ -607,8 +612,10 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
if (UseMI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)
continue;
}
- MRI.setType(DstReg, IsDstPtr ? LLT::pointer(0, GR->getPointerSize())
- : LLT::scalar(32));
+ if (IsDstPtr)
+ MRI.setType(DstReg, LLT::pointer(0, GR->getPointerSize()));
+// MRI.setType(DstReg, IsDstPtr ? LLT::pointer(0, GR->getPointerSize())
+// : LLT::scalar(32));
}
}
}
>From e05c814c50af797f7dc1e293aceb5384cae83ba6 Mon Sep 17 00:00:00 2001
From: "Levytskyy, Vyacheslav" <vyacheslav.levytskyy at intel.com>
Date: Mon, 5 Aug 2024 09:44:19 -0700
Subject: [PATCH 3/3] further improvement of virtual register type/class
settings
---
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 14 ++--
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 3 +-
llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 21 +++++
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 11 ++-
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 66 ++++++++++++---
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 82 ++++++++++++-------
llvm/test/CodeGen/SPIRV/lshr-constexpr.ll | 22 +++--
.../transcoding/OpVectorInsertDynamic_i16.ll | 36 ++++----
8 files changed, 176 insertions(+), 79 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index e70ddc4d39455..4e779f55aae02 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -214,7 +214,7 @@ SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType,
// TODO: https://github.com/llvm/llvm-project/issues/88129
LLT LLTy = LLT::scalar(32);
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
- CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ CurMF->getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
if (MIRBuilder)
assignTypeToVReg(LLVMFloatTy, Res, *MIRBuilder);
else
@@ -354,7 +354,7 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
Register Res = DT.find(ConstFP, &MF);
if (!Res.isValid()) {
Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(32));
- MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
+ MF.getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
assignSPIRVTypeToVReg(SpvType, Res, MF);
DT.add(ConstFP, &MF, Res);
@@ -372,7 +372,8 @@ Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
MachineInstr &I,
SPIRVType *SpvType,
const SPIRVInstrInfo &TII,
- unsigned BitWidth) {
+ unsigned BitWidth,
+ bool ZeroAsNull) {
SPIRVType *Type = SpvType;
if (SpvType->getOpcode() == SPIRV::OpTypeVector ||
SpvType->getOpcode() == SPIRV::OpTypeArray) {
@@ -382,12 +383,12 @@ Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
if (Type->getOpcode() == SPIRV::OpTypeFloat) {
SPIRVType *SpvBaseType = getOrCreateSPIRVFloatType(BitWidth, I, TII);
return getOrCreateConstFP(dyn_cast<ConstantFP>(Val)->getValue(), I,
- SpvBaseType, TII);
+ SpvBaseType, TII, ZeroAsNull);
}
assert(Type->getOpcode() == SPIRV::OpTypeInt);
SPIRVType *SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
return getOrCreateConstInt(Val->getUniqueInteger().getSExtValue(), I,
- SpvBaseType, TII);
+ SpvBaseType, TII, ZeroAsNull);
}
Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
@@ -404,7 +405,8 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
// TODO: can moved below once sorting of types/consts/defs is implemented.
Register SpvScalConst;
if (!IsNull)
- SpvScalConst = getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth);
+ SpvScalConst =
+ getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth, ZeroAsNull);
// TODO: handle cases where the type is not 32bit wide
// TODO: https://github.com/llvm/llvm-project/issues/88129
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index 0e26b38225f7a..09377794da8ba 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -440,7 +440,8 @@ class SPIRVGlobalRegistry {
Register getOrCreateBaseRegister(Constant *Val, MachineInstr &I,
SPIRVType *SpvType,
const SPIRVInstrInfo &TII,
- unsigned BitWidth);
+ unsigned BitWidth,
+ bool ZeroAsNull);
Register getOrCreateCompositeOrNull(Constant *Val, MachineInstr &I,
SPIRVType *SpvType,
const SPIRVInstrInfo &TII, Constant *CA,
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index ae4e039744286..e8e37c4529d49 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -329,6 +329,27 @@ void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const {
return;
MachineRegisterInfo *MRI = &MF.getRegInfo();
+/*
+ // Try to find redundant copies between virtual registers of the same class.
+ for (MachineBasicBlock &MBB : MF) {
+ if (MBB.empty())
+ continue;
+ bool ReachedBegin = false;
+ for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
+ MachineInstr &MI = *MII;
+ if (MII == Begin)
+ ReachedBegin = true;
+ else
+ --MII;
+ if (MI.getOpcode() != TargetOpcode::COPY)
+ continue;
+ Register SrcReg = MI.getOperand(1).getReg();
+ Register DstReg = MI.getOperand(0).getReg();
+ MRI->replaceRegWith(DstReg, SrcReg);
+ MI.eraseFromParent();
+ }
+ }
+*/
SPIRVGlobalRegistry &GR = *STI.getSPIRVGlobalRegistry();
GR.setCurrentFunc(MF);
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 63549b06e9670..8b472fa6e584a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -242,8 +242,8 @@ def ConstPseudoNull: IntImmLeaf<i64, [{ return Imm.isZero(); }]>;
multiclass IntFPImm<bits<16> opCode, string name> {
def I: Op<opCode, (outs ID:$dst), (ins TYPE:$type, ID:$src, variable_ops),
"$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
- def F: Op<opCode, (outs ID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
- "$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
+ def F: Op<opCode, (outs fID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
+ "$dst = "#name#" $type", [(set fID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
}
def OpConstantTrue: Op<41, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
@@ -258,8 +258,9 @@ def OpConstantComposite: Op<44, (outs ID:$res), (ins TYPE:$type, variable_ops),
def OpConstantSampler: Op<45, (outs ID:$res),
(ins TYPE:$t, SamplerAddressingMode:$s, i32imm:$p, SamplerFilterMode:$f),
"$res = OpConstantSampler $t $s $p $f">;
-def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty",
- [(set ID:$dst, (assigntype ConstPseudoNull, TYPE:$src_ty))]>;
+//def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty",
+// [(set ID:$dst, (assigntype ConstPseudoNull, TYPE:$src_ty))]>;
+def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty">;
def OpSpecConstantTrue: Op<48, (outs ID:$r), (ins TYPE:$t), "$r = OpSpecConstantTrue $t">;
def OpSpecConstantFalse: Op<49, (outs ID:$r), (ins TYPE:$t), "$r = OpSpecConstantFalse $t">;
@@ -471,6 +472,8 @@ def OpConvertBF16ToFINTEL : UnOp<"OpConvertBF16ToFINTEL", 6117>;
def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
"$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
+//def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, ID:$vec, ID:$idx),
+// "$res = OpVectorExtractDynamic $type $vec $idx">;
def OpVectorInsertDynamic: Op<78, (outs ID:$res), (ins TYPE:$ty, ID:$vec, ID:$comp, ID:$idx),
"$res = OpVectorInsertDynamic $ty $vec $comp $idx">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 6cb68c98ec3aa..b794a847963d3 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -294,23 +294,61 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
return;
HasVRegsReset = &MF;
+ /*
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
+ Register Reg = Register::index2VirtReg(I);
+ MachineInstr *Def = MRI.getVRegDef(Reg);
+ LLT Ty = MRI.getType(Reg);
+ const TargetRegisterClass *RegClass = MRI.getRegClassOrNull(Reg);
+ if (Ty.isScalar() && (RegClass == &SPIRV::IDRegClass || RegClass ==
+ &SPIRV::ANYIDRegClass)) MRI.setType(Reg, LLT::scalar(32)); if (Def &&
+ Def->getOpcode() == SPIRV::ASSIGN_TYPE) { Register SrcReg =
+ Def->getOperand(1).getReg();
+ //MRI.setType(Reg, LLT::scalar(32));
+ MRI.setType(Reg, MRI.getType(SrcReg));
+ MRI.setRegClass(Reg, &SPIRV::ANYIDRegClass);
+ //MRI.setType(SrcReg, LLT::scalar(32));
+ //MRI.setRegClass(SrcReg, &SPIRV::IDRegClass);
+ } else {
+ //if (Ty.isScalar()) // unsigned Bits = Ty.getScalarSizeInBits();
+ // MRI.setType(Reg, LLT::scalar(32));
+ } // G_FCONSTANT
+ }
+ */
MachineRegisterInfo &MRI = MF.getRegInfo();
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
Register Reg = Register::index2VirtReg(I);
LLT Ty = MRI.getType(Reg);
- if (Ty.isScalar()) {
- unsigned Bits = Ty.getScalarSizeInBits();
- switch (Bits) {
- //case 1:
- case 32:
- break;
- default:
- MRI.setType(Reg, LLT::scalar(32));
- }
- } else if (!Ty.isPointer()) {
- if (auto *Def = MRI.getVRegDef(Reg))
- if (Def->getOpcode() == SPIRV::ASSIGN_TYPE)
+ if (Ty.isScalar())
+ MRI.setType(Reg, LLT::scalar(32));
+ else if (Ty.isVector() && !Ty.isPointer())
+ MRI.setType(Reg, LLT::scalar(32));
+ //MRI.setType(Reg, LLT::fixed_vector(2, LLT::scalar(32)));
+ /* auto *Def = MRI.getVRegDef(Reg));
+ if (!Def)
+ continue;
+ if (Def->getOpcode() == SPIRV::ASSIGN_TYPE) {
+ Register SrcReg = Def->getOperand(1).getReg();
MRI.setType(Reg, LLT::scalar(32));
+ }*/
+ }
+ for (const auto &MBB : MF) {
+ for (const auto &MI : MBB) {
+ if (MI.getOpcode() != SPIRV::ASSIGN_TYPE)
+ continue;
+ Register DstReg = MI.getOperand(0).getReg();
+ LLT DstType = MRI.getType(DstReg);
+ Register SrcReg = MI.getOperand(1).getReg();
+ LLT SrcType = MRI.getType(SrcReg);
+ if (DstType != SrcType)
+ MRI.setType(DstReg, MRI.getType(SrcReg));
+
+ const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
+ const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(SrcReg);
+ if (DstRC != SrcRC && SrcRC)
+ MRI.setRegClass(DstReg, SrcRC);
+ //MRI.setType(Reg, LLT::scalar(32));
}
}
}
@@ -337,10 +375,14 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
if (MRI->getType(DstReg).isPointer())
MRI->setType(DstReg, LLT::scalar(32));
bool Res = selectImpl(I, *CoverageInfo);
+ if (!Res && Def->getOpcode() != TargetOpcode::G_CONSTANT) {
+ I.dump();
+ }
assert(Res || Def->getOpcode() == TargetOpcode::G_CONSTANT);
if (Res)
return Res;
}
+ MRI->setRegClass(DstReg, &SPIRV::IDRegClass);
MRI->replaceRegWith(SrcReg, DstReg);
I.removeFromParent();
return true;
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 6323fcfbe8051..0bc904223f8c5 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -225,17 +225,17 @@ static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR,
static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
MachineRegisterInfo &MRI,
MachineIRBuilder &MIB) {
- SPIRVType *SpirvTy = nullptr;
+ SPIRVType *SpvType = nullptr;
assert(MI && "Machine instr is expected");
if (MI->getOperand(0).isReg()) {
Register Reg = MI->getOperand(0).getReg();
- SpirvTy = GR->getSPIRVTypeForVReg(Reg);
- if (!SpirvTy) {
+ SpvType = GR->getSPIRVTypeForVReg(Reg);
+ if (!SpvType) {
switch (MI->getOpcode()) {
case TargetOpcode::G_CONSTANT: {
MIB.setInsertPt(*MI->getParent(), MI);
Type *Ty = MI->getOperand(1).getCImm()->getType();
- SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB);
+ SpvType = GR->getOrCreateSPIRVType(Ty, MIB);
break;
}
case TargetOpcode::G_GLOBAL_VALUE: {
@@ -244,7 +244,7 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
Type *ElementTy = toTypedPointer(GR->getDeducedGlobalValueType(Global));
auto *Ty = TypedPointerType::get(ElementTy,
Global->getType()->getAddressSpace());
- SpirvTy = GR->getOrCreateSPIRVType(Ty, MIB);
+ SpvType = GR->getOrCreateSPIRVType(Ty, MIB);
break;
}
case TargetOpcode::G_ANYEXT:
@@ -258,17 +258,17 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
unsigned ExpectedBW =
std::max(MRI.getType(Reg).getScalarSizeInBits(), CurrentBW);
unsigned NumElements = GR->getScalarOrVectorComponentCount(Def);
- SpirvTy = GR->getOrCreateSPIRVIntegerType(ExpectedBW, MIB);
+ SpvType = GR->getOrCreateSPIRVIntegerType(ExpectedBW, MIB);
if (NumElements > 1)
- SpirvTy =
- GR->getOrCreateSPIRVVectorType(SpirvTy, NumElements, MIB);
+ SpvType =
+ GR->getOrCreateSPIRVVectorType(SpvType, NumElements, MIB);
}
}
}
break;
}
case TargetOpcode::G_PTRTOINT:
- SpirvTy = GR->getOrCreateSPIRVIntegerType(
+ SpvType = GR->getOrCreateSPIRVIntegerType(
MRI.getType(Reg).getScalarSizeInBits(), MIB);
break;
case TargetOpcode::G_TRUNC:
@@ -278,19 +278,19 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
MachineOperand &Op = MI->getOperand(1);
MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr;
if (Def)
- SpirvTy = propagateSPIRVType(Def, GR, MRI, MIB);
+ SpvType = propagateSPIRVType(Def, GR, MRI, MIB);
break;
}
default:
break;
}
- if (SpirvTy)
- GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
+ if (SpvType)
+ GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
if (!MRI.getRegClassOrNull(Reg))
MRI.setRegClass(Reg, &SPIRV::IDRegClass);
}
}
- return SpirvTy;
+ return SpvType;
}
// To support current approach and limitations wrt. bit width here we widen a
@@ -316,6 +316,30 @@ inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
->getOpcode() == SPIRV::OpTypeFloat;
}
+static const TargetRegisterClass *getRegClass(SPIRVType *SpvType,
+ const SPIRVGlobalRegistry &GR) {
+ unsigned Opcode = SpvType->getOpcode();
+ switch (Opcode) {
+ case SPIRV::OpTypeFloat:
+ return &SPIRV::fIDRegClass;
+ case SPIRV::OpTypePointer:
+ return GR.getPointerSize() == 64 ? &SPIRV::pID64RegClass
+ : &SPIRV::pID32RegClass;
+ case SPIRV::OpTypeVector: {
+ SPIRVType *ElemType =
+ GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
+ unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;
+ if (ElemOpcode == SPIRV::OpTypeFloat)
+ return &SPIRV::vfIDRegClass;
+ if (ElemOpcode == SPIRV::OpTypePointer)
+ return GR.getPointerSize() == 64 ? &SPIRV::vpID64RegClass
+ : &SPIRV::vpID32RegClass;
+ return &SPIRV::vIDRegClass;
+ }
+ }
+ return &SPIRV::IDRegClass;
+}
+
static std::pair<Register, unsigned>
createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
const SPIRVGlobalRegistry &GR) {
@@ -326,7 +350,9 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
LLT NewT;
bool IsFloat = getIsFloat(SpvType, GR);
auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
- auto DstClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
+ auto DstClass =
+ IsFloat ? &SPIRV::fIDRegClass
+ : &SPIRV::IDRegClass; // TODO: call getRegClass(SpvType, GR)
if (SrcLLT.isPointer()) {
unsigned PtrSz = GR.getPointerSize();
NewT = LLT::pointer(0, PtrSz);
@@ -351,8 +377,9 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
}
}
} else if (SrcLLT.isVector()) {
- NewT = LLT::scalar(32); //LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
- NewT = LLT::fixed_vector(2, NewT);
+ NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
+ NewT =
+ LLT::fixed_vector(2, NewT); // TODO: use actual vector size instead of 2
if (IsFloat) {
GetIdOp = SPIRV::GET_vfID;
DstClass = &SPIRV::vfIDRegClass;
@@ -369,40 +396,39 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
}
// Insert ASSIGN_TYPE instuction between Reg and its definition, set NewReg as
-// a dst of the definition, assign SPIRVType to both registers. If SpirvTy is
+// a dst of the definition, assign SPIRVType to both registers. If SpvType is
// provided, use it as SPIRVType in ASSIGN_TYPE, otherwise create it from Ty.
// It's used also in SPIRVBuiltins.cpp.
// TODO: maybe move to SPIRVUtils.
namespace llvm {
-Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy,
+Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpvType,
SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) {
MachineInstr *Def = MRI.getVRegDef(Reg);
- assert((Ty || SpirvTy) && "Either LLVM or SPIRV type is expected.");
+ assert((Ty || SpvType) && "Either LLVM or SPIRV type is expected.");
MIB.setInsertPt(*Def->getParent(),
(Def->getNextNode() ? Def->getNextNode()->getIterator()
: Def->getParent()->end()));
- SpirvTy = SpirvTy ? SpirvTy : GR->getOrCreateSPIRVType(Ty, MIB);
+ SpvType = SpvType ? SpvType : GR->getOrCreateSPIRVType(Ty, MIB);
Register NewReg = MRI.createGenericVirtualRegister(MRI.getType(Reg));
if (auto *RC = MRI.getRegClassOrNull(Reg)) {
MRI.setRegClass(NewReg, RC);
} else {
- bool IsFloat = false;//getIsFloat(SpirvTy, *GR);
- auto RegClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass;
+ auto RegClass = getRegClass(SpvType, *GR);
MRI.setRegClass(NewReg, RegClass);
MRI.setRegClass(Reg, RegClass);
}
- GR->assignSPIRVTypeToVReg(SpirvTy, Reg, MIB.getMF());
+ GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
// This is to make it convenient for Legalizer to get the SPIRVType
// when processing the actual MI (i.e. not pseudo one).
- GR->assignSPIRVTypeToVReg(SpirvTy, NewReg, MIB.getMF());
+ GR->assignSPIRVTypeToVReg(SpvType, NewReg, MIB.getMF());
// Copy MIFlags from Def to ASSIGN_TYPE instruction. It's required to keep
// the flags after instruction selection.
const uint32_t Flags = Def->getFlags();
MIB.buildInstr(SPIRV::ASSIGN_TYPE)
.addDef(Reg)
.addUse(NewReg)
- .addUse(GR->getSPIRVTypeID(SpirvTy))
+ .addUse(GR->getSPIRVTypeID(SpvType))
.setMIFlags(Flags);
Def->getOperand(0).setReg(NewReg);
return NewReg;
@@ -603,8 +629,8 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
Register DstReg = MI.getOperand(0).getReg();
bool IsDstPtr = MRI.getType(DstReg).isPointer();
bool isDstVec = MRI.getType(DstReg).isVector();
- if (IsDstPtr || isDstVec)
- MRI.setRegClass(DstReg, &SPIRV::IDRegClass);
+// if (IsDstPtr || isDstVec)
+// MRI.setRegClass(DstReg, &SPIRV::IDRegClass);
// Don't need to reset type of register holding constant and used in
// G_ADDRSPACE_CAST, since it breaks legalizer.
if (Opcode == TargetOpcode::G_CONSTANT && MRI.hasOneUse(DstReg)) {
@@ -614,8 +640,6 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
}
if (IsDstPtr)
MRI.setType(DstReg, LLT::pointer(0, GR->getPointerSize()));
-// MRI.setType(DstReg, IsDstPtr ? LLT::pointer(0, GR->getPointerSize())
-// : LLT::scalar(32));
}
}
}
diff --git a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
index 44b11f3ddb273..f2f97f56263f9 100644
--- a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
+++ b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll
@@ -1,14 +1,18 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV-DAG: %[[#type_int32:]] = OpTypeInt 32 0
-; CHECK-SPIRV-DAG: %[[#type_int64:]] = OpTypeInt 64 0
-; CHECK-SPIRV: %[[#type_vec:]] = OpTypeVector %[[#type_int32]] 2
-; CHECK-SPIRV: %[[#const1:]] = OpConstant %[[#type_int32]] 1
-; CHECK-SPIRV: %[[#vec_const:]] = OpConstantComposite %[[#type_vec]] %[[#const1]] %[[#const1]]
-; CHECK-SPIRV: %[[#const32:]] = OpConstant %[[#type_int64]] 32
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV: %[[#bitcast_res:]] = OpBitcast %[[#type_int64]] %[[#vec_const]]
-; CHECK-SPIRV: %[[#shift_res:]] = OpShiftRightLogical %[[#type_int64]] %[[#bitcast_res]] %[[#const32]]
+; CHECK-DAG: %[[#type_int32:]] = OpTypeInt 32 0
+; CHECK-DAG: %[[#type_int64:]] = OpTypeInt 64 0
+; CHECK-DAG: %[[#type_vec:]] = OpTypeVector %[[#type_int32]] 2
+; CHECK-DAG: %[[#const1:]] = OpConstant %[[#type_int32]] 1
+; CHECK-DAG: %[[#vec_const:]] = OpConstantComposite %[[#type_vec]] %[[#const1]] %[[#const1]]
+; CHECK-DAG: %[[#const32:]] = OpConstant %[[#type_int64]] 32
+
+; CHECK: %[[#bitcast_res:]] = OpBitcast %[[#type_int64]] %[[#vec_const]]
+; CHECK: %[[#shift_res:]] = OpShiftRightLogical %[[#type_int64]] %[[#bitcast_res]] %[[#const32]]
define void @foo(i64* %arg) {
entry:
diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
index cb41aad2a0c5f..0e66f2d22a3ff 100644
--- a/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
+++ b/llvm/test/CodeGen/SPIRV/transcoding/OpVectorInsertDynamic_i16.ll
@@ -1,23 +1,23 @@
-; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV: OpName %[[#v:]] "v"
-; CHECK-SPIRV: OpName %[[#index:]] "index"
-; CHECK-SPIRV: OpName %[[#res:]] "res"
+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
-; CHECK-SPIRV-DAG: %[[#int16:]] = OpTypeInt 16
-; CHECK-SPIRV-DAG: %[[#int32:]] = OpTypeInt 32
-; CHECK-SPIRV-DAG: %[[#int16_2:]] = OpTypeVector %[[#int16]] 2
-
-; CHECK-SPIRV: %[[#undef:]] = OpUndef %[[#int16_2]]
-
-; CHECK-SPIRV-DAG: %[[#const1:]] = OpConstant %[[#int16]] 4
-; CHECK-SPIRV-DAG: %[[#const2:]] = OpConstant %[[#int16]] 8
-; CHECK-SPIRV-NOT: %[[#idx1:]] = OpConstant %[[#int32]] 0
-; CHECK-SPIRV-NOT: %[[#idx2:]] = OpConstant %[[#int32]] 1
-
-; CHECK-SPIRV: %[[#vec1:]] = OpCompositeInsert %[[#int16_2]] %[[#const1]] %[[#undef]] 0
-; CHECK-SPIRV: %[[#vec2:]] = OpCompositeInsert %[[#int16_2]] %[[#const2]] %[[#vec1]] 1
-; CHECK-SPIRV: %[[#res]] = OpVectorInsertDynamic %[[#int16_2]] %[[#vec2]] %[[#v]] %[[#index]]
+; CHECK: OpName %[[#v:]] "v"
+; CHECK: OpName %[[#index:]] "index"
+; CHECK: OpName %[[#res:]] "res"
+; CHECK-DAG: %[[#int16:]] = OpTypeInt 16
+; CHECK-DAG: %[[#int32:]] = OpTypeInt 32
+; CHECK-DAG: %[[#int16_2:]] = OpTypeVector %[[#int16]] 2
+; CHECK-DAG: %[[#undef:]] = OpUndef %[[#int16_2]]
+; CHECK-DAG: %[[#const1:]] = OpConstant %[[#int16]] 4
+; CHECK-DAG: %[[#const2:]] = OpConstant %[[#int16]] 8
+; CHECK-NOT: %[[#idx1:]] = OpConstant %[[#int32]] 0
+; CHECK-NOT: %[[#idx2:]] = OpConstant %[[#int32]] 1
+; CHECK: %[[#vec1:]] = OpCompositeInsert %[[#int16_2]] %[[#const1]] %[[#undef]] 0
+; CHECK: %[[#vec2:]] = OpCompositeInsert %[[#int16_2]] %[[#const2]] %[[#vec1]] 1
+; CHECK: %[[#res]] = OpVectorInsertDynamic %[[#int16_2]] %[[#vec2]] %[[#v]] %[[#index]]
define spir_kernel void @test(<2 x i16>* nocapture %out, i16 %v, i32 %index) {
entry:
More information about the llvm-commits
mailing list