[llvm] [SPIRV] Add sign intrinsic part 1 (PR #101987)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff 04f65043bc8711996a4ade05c67ae2d087ae8be5 def83841c2b72e66a374de3182deb67a9e498325 --extensions cpp -- llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index cdbee67c87..47e4b3dd40 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -180,7 +180,7 @@ private:
                    MachineInstr &I) const;
 
   bool selectSign(Register ResVReg, const SPIRVType *ResType,
-                   MachineInstr &I) const;
+                  MachineInstr &I) const;
 
   void renderImm32(MachineInstrBuilder &MIB, const MachineInstr &I,
                    int OpIdx) const;
@@ -1391,7 +1391,9 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg,
   bool NeedsConversion = IsFloatTy || SignBitWidth != ResBitWidth;
 
   auto SignOpcode = IsFloatTy ? GL::FSign : GL::SSign;
-  Register SignReg = NeedsConversion ? MRI->createVirtualRegister(&SPIRV::IDRegClass) : ResVReg;
+  Register SignReg = NeedsConversion
+                         ? MRI->createVirtualRegister(&SPIRV::IDRegClass)
+                         : ResVReg;
 
   bool Result =
       BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst))

``````````

</details>


https://github.com/llvm/llvm-project/pull/101987