[llvm] [SelectionDAG] Simplify vselect true, T, F -> T (PR #100992)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 5 04:49:30 PDT 2024
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/100992
>From 52d1103acba7ada6632f45b0fd774ff5de19e939 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 29 Jul 2024 17:02:13 +0800
Subject: [PATCH 1/8] Precommit tests
---
llvm/test/CodeGen/RISCV/rvv/vp-select.ll | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vp-select.ll
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-select.ll b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
new file mode 100644
index 0000000000000..a218230e126d7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
+
+define <vscale x 1 x i64> @all_ones(<vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl) {
+; CHECK-LABEL: all_ones:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 32
+; CHECK-NEXT: srli a0, a0, 32
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vmv.v.v v9, v8
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1> splat (i1 true), <vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl)
+ ret <vscale x 1 x i64> %v
+}
>From 4efe9db41bce77dc626e2a432020b08b14c6d494 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 29 Jul 2024 17:11:25 +0800
Subject: [PATCH 2/8] [SelectionDAG] Simplify vselect true, T, F -> T
This addresses a TODO where we can fold a vselect to it's true operand if the boolean is known to be all trues, checking getBooleanContents.
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 20 ++++++++++++++++---
llvm/test/CodeGen/RISCV/rvv/vp-select.ll | 5 -----
2 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index daebcdabda984..1876bf3f18c21 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -9927,13 +9927,27 @@ SDValue SelectionDAG::simplifySelect(SDValue Cond, SDValue T, SDValue F) {
if (auto *CondC = dyn_cast<ConstantSDNode>(Cond))
return CondC->isZero() ? F : T;
- // TODO: This should simplify VSELECT with non-zero constant condition using
- // something like this (but check boolean contents to be complete?):
if (ConstantSDNode *CondC = isConstOrConstSplat(Cond, /*AllowUndefs*/ false,
- /*AllowTruncation*/ true))
+ /*AllowTruncation*/ true)) {
if (CondC->isZero())
return F;
+ switch (TLI->getBooleanContents(Cond.getValueType())) {
+ case TargetLowering::UndefinedBooleanContent:
+ if (CondC->getAPIntValue()[0])
+ return T;
+ break;
+ case TargetLowering::ZeroOrOneBooleanContent:
+ if (CondC->isOne())
+ return T;
+ break;
+ case TargetLowering::ZeroOrNegativeOneBooleanContent:
+ if (CondC->isAllOnes())
+ return T;
+ break;
+ }
+ }
+
// select ?, T, T --> T
if (T == F)
return T;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-select.ll b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
index a218230e126d7..5c903791927c6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
@@ -4,11 +4,6 @@
define <vscale x 1 x i64> @all_ones(<vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl) {
; CHECK-LABEL: all_ones:
; CHECK: # %bb.0:
-; CHECK-NEXT: slli a0, a0, 32
-; CHECK-NEXT: srli a0, a0, 32
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
-; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1> splat (i1 true), <vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl)
ret <vscale x 1 x i64> %v
>From 7417903a6c15bab9f3064db0738483aa1bb04a77 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 29 Jul 2024 18:05:38 +0800
Subject: [PATCH 3/8] Extract out isBoolConstant
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 5 +++
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 21 ++--------
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 42 +++++++++----------
3 files changed, 27 insertions(+), 41 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 6a80c8c7216f6..5035e298081fe 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -2320,6 +2320,11 @@ class SelectionDAG {
isConstantFPBuildVectorOrConstantFP(N);
}
+ /// Check if a value \op N is a true or false constant using the target's
+ /// BooleanContent for its type.
+ std::optional<bool> isBoolConstant(SDValue N,
+ bool AllowTruncation = false) const;
+
/// Set CallSiteInfo to be associated with Node.
void addCallSiteInfo(const SDNode *Node, CallSiteInfo &&CallInfo) {
SDEI[Node].CSInfo = std::move(CallInfo);
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 060e66175d965..27bdab3d83833 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3260,26 +3260,11 @@ static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG,
if (V.getOpcode() != ISD::XOR)
return SDValue();
- ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false);
- if (!Const)
+ auto IsFlip = DAG.isBoolConstant(V.getOperand(1));
+ if (!IsFlip)
return SDValue();
- EVT VT = V.getValueType();
-
- bool IsFlip = false;
- switch(TLI.getBooleanContents(VT)) {
- case TargetLowering::ZeroOrOneBooleanContent:
- IsFlip = Const->isOne();
- break;
- case TargetLowering::ZeroOrNegativeOneBooleanContent:
- IsFlip = Const->isAllOnes();
- break;
- case TargetLowering::UndefinedBooleanContent:
- IsFlip = (Const->getAPIntValue() & 0x01) == 1;
- break;
- }
-
- if (IsFlip)
+ if (*IsFlip)
return V.getOperand(0);
if (Force)
return DAG.getLogicalNOT(SDLoc(V), V, V.getValueType());
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1876bf3f18c21..cc55cefcb376a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -9924,29 +9924,8 @@ SDValue SelectionDAG::simplifySelect(SDValue Cond, SDValue T, SDValue F) {
// select true, T, F --> T
// select false, T, F --> F
- if (auto *CondC = dyn_cast<ConstantSDNode>(Cond))
- return CondC->isZero() ? F : T;
-
- if (ConstantSDNode *CondC = isConstOrConstSplat(Cond, /*AllowUndefs*/ false,
- /*AllowTruncation*/ true)) {
- if (CondC->isZero())
- return F;
-
- switch (TLI->getBooleanContents(Cond.getValueType())) {
- case TargetLowering::UndefinedBooleanContent:
- if (CondC->getAPIntValue()[0])
- return T;
- break;
- case TargetLowering::ZeroOrOneBooleanContent:
- if (CondC->isOne())
- return T;
- break;
- case TargetLowering::ZeroOrNegativeOneBooleanContent:
- if (CondC->isAllOnes())
- return T;
- break;
- }
- }
+ if (auto CondC = isBoolConstant(Cond, /*AllowTruncation*/ true))
+ return *CondC ? T : F;
// select ?, T, T --> T
if (T == F)
@@ -13138,6 +13117,23 @@ SDNode *SelectionDAG::isConstantFPBuildVectorOrConstantFP(SDValue N) const {
return nullptr;
}
+std::optional<bool> SelectionDAG::isBoolConstant(SDValue N,
+ bool AllowTruncation) const {
+ ConstantSDNode *Const = isConstOrConstSplat(N, false, AllowTruncation);
+ if (!Const)
+ return std::nullopt;
+
+ switch (TLI->getBooleanContents(N.getValueType())) {
+ case TargetLowering::ZeroOrOneBooleanContent:
+ return Const->isOne();
+ case TargetLowering::ZeroOrNegativeOneBooleanContent:
+ return Const->isAllOnes();
+ break;
+ case TargetLowering::UndefinedBooleanContent:
+ return Const->getAPIntValue()[0];
+ }
+}
+
void SelectionDAG::createOperands(SDNode *Node, ArrayRef<SDValue> Vals) {
assert(!Node->OperandList && "Node already has operands");
assert(SDNode::getMaxNumOperands() >= Vals.size() &&
>From 15400c147cd181ece55f9db6141e6cad79781e66 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 29 Jul 2024 19:05:04 +0800
Subject: [PATCH 4/8] Add all false test
---
llvm/test/CodeGen/RISCV/rvv/vp-select.ll | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-select.ll b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
index 5c903791927c6..c8a048971a803 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-select.ll
@@ -8,3 +8,12 @@ define <vscale x 1 x i64> @all_ones(<vscale x 1 x i64> %true, <vscale x 1 x i64>
%v = call <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1> splat (i1 true), <vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl)
ret <vscale x 1 x i64> %v
}
+
+define <vscale x 1 x i64> @all_zeroes(<vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl) {
+; CHECK-LABEL: all_zeroes:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmv1r.v v8, v9
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1> splat (i1 false), <vscale x 1 x i64> %true, <vscale x 1 x i64> %false, i32 %evl)
+ ret <vscale x 1 x i64> %v
+}
>From 4552d3047dd40d347d280c2b0cc439df1affa080 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 29 Jul 2024 19:05:47 +0800
Subject: [PATCH 5/8] Add equals to comment
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index cc55cefcb376a..27dd9870757b3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -9924,7 +9924,7 @@ SDValue SelectionDAG::simplifySelect(SDValue Cond, SDValue T, SDValue F) {
// select true, T, F --> T
// select false, T, F --> F
- if (auto CondC = isBoolConstant(Cond, /*AllowTruncation*/ true))
+ if (auto CondC = isBoolConstant(Cond, /*AllowTruncation=*/ true))
return *CondC ? T : F;
// select ?, T, T --> T
>From 4eee8f51a171c83d05faa3855ec43cd85a35bd3c Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 29 Jul 2024 19:11:11 +0800
Subject: [PATCH 6/8] clang-format
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 27dd9870757b3..0266846620645 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -9924,7 +9924,7 @@ SDValue SelectionDAG::simplifySelect(SDValue Cond, SDValue T, SDValue F) {
// select true, T, F --> T
// select false, T, F --> F
- if (auto CondC = isBoolConstant(Cond, /*AllowTruncation=*/ true))
+ if (auto CondC = isBoolConstant(Cond, /*AllowTruncation=*/true))
return *CondC ? T : F;
// select ?, T, T --> T
>From 4de34ee0ac49a9b6bca4a43485fa9ebc77e04667 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 29 Jul 2024 23:01:47 +0800
Subject: [PATCH 7/8] Add Valuev arg to isBoolConstant, restore
extractBooleanFlip behaviour if operand isn't constant, update tests on other
targets
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 6 +--
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 5 +--
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 19 +++++----
.../CodeGen/AArch64/srem-seteq-vec-splat.ll | 2 +-
llvm/test/CodeGen/X86/combine-srem.ll | 40 ++++++++++---------
llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll | 6 +--
6 files changed, 42 insertions(+), 36 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 5035e298081fe..2d24ae5681388 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -2320,10 +2320,10 @@ class SelectionDAG {
isConstantFPBuildVectorOrConstantFP(N);
}
- /// Check if a value \op N is a true or false constant using the target's
+ /// Check if a value \op N is a \op Value constant using the target's
/// BooleanContent for its type.
- std::optional<bool> isBoolConstant(SDValue N,
- bool AllowTruncation = false) const;
+ bool isBoolConstant(SDValue N, bool Value,
+ bool AllowTruncation = false) const;
/// Set CallSiteInfo to be associated with Node.
void addCallSiteInfo(const SDNode *Node, CallSiteInfo &&CallInfo) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 27bdab3d83833..2ef3efdb76c54 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3260,11 +3260,10 @@ static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG,
if (V.getOpcode() != ISD::XOR)
return SDValue();
- auto IsFlip = DAG.isBoolConstant(V.getOperand(1));
- if (!IsFlip)
+ if (!isConstOrConstSplat(V.getOperand(1), false))
return SDValue();
- if (*IsFlip)
+ if (DAG.isBoolConstant(V.getOperand(1), true))
return V.getOperand(0);
if (Force)
return DAG.getLogicalNOT(SDLoc(V), V, V.getValueType());
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 0266846620645..c98358a4bd8a0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -9923,9 +9923,11 @@ SDValue SelectionDAG::simplifySelect(SDValue Cond, SDValue T, SDValue F) {
return T;
// select true, T, F --> T
+ if (isBoolConstant(Cond, true, /*AllowTruncation=*/true))
+ return T;
// select false, T, F --> F
- if (auto CondC = isBoolConstant(Cond, /*AllowTruncation=*/true))
- return *CondC ? T : F;
+ if (isBoolConstant(Cond, false, /*AllowTruncation=*/true))
+ return F;
// select ?, T, T --> T
if (T == F)
@@ -13117,20 +13119,21 @@ SDNode *SelectionDAG::isConstantFPBuildVectorOrConstantFP(SDValue N) const {
return nullptr;
}
-std::optional<bool> SelectionDAG::isBoolConstant(SDValue N,
- bool AllowTruncation) const {
+bool SelectionDAG::isBoolConstant(SDValue N, bool Value,
+ bool AllowTruncation) const {
ConstantSDNode *Const = isConstOrConstSplat(N, false, AllowTruncation);
if (!Const)
- return std::nullopt;
+ return false;
+ const APInt &CVal = Const->getAPIntValue();
switch (TLI->getBooleanContents(N.getValueType())) {
case TargetLowering::ZeroOrOneBooleanContent:
- return Const->isOne();
+ return Value ? CVal.isOne() : CVal.isZero();
case TargetLowering::ZeroOrNegativeOneBooleanContent:
- return Const->isAllOnes();
+ return Value ? CVal.isAllOnes() : CVal.isZero();
break;
case TargetLowering::UndefinedBooleanContent:
- return Const->getAPIntValue()[0];
+ return Value ? CVal[0] : !CVal[0];
}
}
diff --git a/llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll b/llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
index c0c0ae5c9d1fe..03d40fc61f0c3 100644
--- a/llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
+++ b/llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
@@ -206,7 +206,7 @@ define <4 x i32> @test_srem_int_min(<4 x i32> %X) nounwind {
; CHECK-NEXT: movi v1.4s, #128, lsl #24
; CHECK-NEXT: usra v3.4s, v2.4s, #1
; CHECK-NEXT: and v1.16b, v3.16b, v1.16b
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
diff --git a/llvm/test/CodeGen/X86/combine-srem.ll b/llvm/test/CodeGen/X86/combine-srem.ll
index 4ed00a9d66bd3..8bfaa6118b791 100644
--- a/llvm/test/CodeGen/X86/combine-srem.ll
+++ b/llvm/test/CodeGen/X86/combine-srem.ll
@@ -83,7 +83,7 @@ define <4 x i32> @combine_vec_srem_by_minsigned(<4 x i32> %x) {
; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vpaddd %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_vec_srem_by_minsigned:
@@ -93,7 +93,7 @@ define <4 x i32> @combine_vec_srem_by_minsigned(<4 x i32> %x) {
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
-; AVX2-NEXT: vpaddd %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
%1 = srem <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
ret <4 x i32> %1
@@ -225,24 +225,28 @@ define <4 x i32> @combine_vec_srem_by_pow2a_neg(<4 x i32> %x) {
; SSE-NEXT: psrad $31, %xmm1
; SSE-NEXT: psrld $30, %xmm1
; SSE-NEXT: paddd %xmm0, %xmm1
-; SSE-NEXT: psrld $2, %xmm1
-; SSE-NEXT: pxor %xmm2, %xmm2
-; SSE-NEXT: psubd %xmm1, %xmm2
-; SSE-NEXT: pslld $2, %xmm2
-; SSE-NEXT: paddd %xmm2, %xmm0
+; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: psubd %xmm1, %xmm0
; SSE-NEXT: retq
;
-; AVX-LABEL: combine_vec_srem_by_pow2a_neg:
-; AVX: # %bb.0:
-; AVX-NEXT: vpsrad $31, %xmm0, %xmm1
-; AVX-NEXT: vpsrld $30, %xmm1, %xmm1
-; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm1
-; AVX-NEXT: vpsrld $2, %xmm1, %xmm1
-; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
-; AVX-NEXT: vpsubd %xmm1, %xmm2, %xmm1
-; AVX-NEXT: vpslld $2, %xmm1, %xmm1
-; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT: retq
+; AVX1-LABEL: combine_vec_srem_by_pow2a_neg:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
+; AVX1-NEXT: vpsrld $30, %xmm1, %xmm1
+; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
+; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
+; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: combine_vec_srem_by_pow2a_neg:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
+; AVX2-NEXT: vpsrld $30, %xmm1, %xmm1
+; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
+; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4294967292,4294967292,4294967292,4294967292]
+; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
+; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: retq
%1 = srem <4 x i32> %x, <i32 -4, i32 -4, i32 -4, i32 -4>
ret <4 x i32> %1
}
diff --git a/llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll b/llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll
index d2a1e5e428129..33592027dee93 100644
--- a/llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll
+++ b/llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll
@@ -624,7 +624,7 @@ define <4 x i32> @test_srem_int_min(<4 x i32> %X) nounwind {
; CHECK-AVX1-NEXT: vpsrld $1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; CHECK-AVX1-NEXT: vpaddd %xmm0, %xmm1, %xmm0
+; CHECK-AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -637,7 +637,7 @@ define <4 x i32> @test_srem_int_min(<4 x i32> %X) nounwind {
; CHECK-AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; CHECK-AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
-; CHECK-AVX2-NEXT: vpaddd %xmm0, %xmm1, %xmm0
+; CHECK-AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
@@ -649,7 +649,7 @@ define <4 x i32> @test_srem_int_min(<4 x i32> %X) nounwind {
; CHECK-AVX512VL-NEXT: vpsrld $1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm1
; CHECK-AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
-; CHECK-AVX512VL-NEXT: vpaddd %xmm0, %xmm1, %xmm0
+; CHECK-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
>From 64f52d9e0879bde64bbdd2f56541ab857609b6c2 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 5 Aug 2024 19:48:31 +0800
Subject: [PATCH 8/8] Move isConstSplat check to Force, change isBoolConstant
to use std::optional
---
llvm/include/llvm/CodeGen/SelectionDAG.h | 8 +++---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 ++---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 27 +++++++++++--------
3 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 2d24ae5681388..1d0124ec75535 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -2320,10 +2320,10 @@ class SelectionDAG {
isConstantFPBuildVectorOrConstantFP(N);
}
- /// Check if a value \op N is a \op Value constant using the target's
- /// BooleanContent for its type.
- bool isBoolConstant(SDValue N, bool Value,
- bool AllowTruncation = false) const;
+ /// Check if a value \op N is a constant using the target's BooleanContent for
+ /// its type.
+ std::optional<bool> isBoolConstant(SDValue N,
+ bool AllowTruncation = false) const;
/// Set CallSiteInfo to be associated with Node.
void addCallSiteInfo(const SDNode *Node, CallSiteInfo &&CallInfo) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2ef3efdb76c54..7ae39e3d2da98 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3260,12 +3260,9 @@ static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG,
if (V.getOpcode() != ISD::XOR)
return SDValue();
- if (!isConstOrConstSplat(V.getOperand(1), false))
- return SDValue();
-
- if (DAG.isBoolConstant(V.getOperand(1), true))
+ if (DAG.isBoolConstant(V.getOperand(1)) == true)
return V.getOperand(0);
- if (Force)
+ if (Force && isConstOrConstSplat(V.getOperand(1), false))
return DAG.getLogicalNOT(SDLoc(V), V, V.getValueType());
return SDValue();
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c98358a4bd8a0..c40a84037bacf 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -9923,11 +9923,9 @@ SDValue SelectionDAG::simplifySelect(SDValue Cond, SDValue T, SDValue F) {
return T;
// select true, T, F --> T
- if (isBoolConstant(Cond, true, /*AllowTruncation=*/true))
- return T;
// select false, T, F --> F
- if (isBoolConstant(Cond, false, /*AllowTruncation=*/true))
- return F;
+ if (auto C = isBoolConstant(Cond, /*AllowTruncation=*/true))
+ return *C ? T : F;
// select ?, T, T --> T
if (T == F)
@@ -13119,21 +13117,28 @@ SDNode *SelectionDAG::isConstantFPBuildVectorOrConstantFP(SDValue N) const {
return nullptr;
}
-bool SelectionDAG::isBoolConstant(SDValue N, bool Value,
- bool AllowTruncation) const {
+std::optional<bool> SelectionDAG::isBoolConstant(SDValue N,
+ bool AllowTruncation) const {
ConstantSDNode *Const = isConstOrConstSplat(N, false, AllowTruncation);
if (!Const)
- return false;
+ return std::nullopt;
const APInt &CVal = Const->getAPIntValue();
switch (TLI->getBooleanContents(N.getValueType())) {
case TargetLowering::ZeroOrOneBooleanContent:
- return Value ? CVal.isOne() : CVal.isZero();
+ if (CVal.isOne())
+ return true;
+ if (CVal.isZero())
+ return false;
+ return std::nullopt;
case TargetLowering::ZeroOrNegativeOneBooleanContent:
- return Value ? CVal.isAllOnes() : CVal.isZero();
- break;
+ if (CVal.isAllOnes())
+ return true;
+ if (CVal.isZero())
+ return false;
+ return std::nullopt;
case TargetLowering::UndefinedBooleanContent:
- return Value ? CVal[0] : !CVal[0];
+ return CVal[0];
}
}
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