[llvm] [X86][RA] Add two address hints for compressible NDD instructions. (PR #98603)

[Shengchen Kan via llvm-commits]

================
@@ -1082,8 +1088,52 @@ bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
       VirtReg, Order, Hints, MF, VRM, Matrix);
 
   unsigned ID = RC.getID();
-  if (ID != X86::TILERegClassID)
+
+  if (!VRM)
+    return BaseImplRetVal;
+
+  if (ID != X86::TILERegClassID) {
----------------
KanRobert wrote:

In order to not introduce compiler-time regression. We should use

```
if (DisableRegAllocNDDHints || !MF.getSubtarget<X86Subtarget>().hasNDD() || !isGPR(RC))
```

See X86DomainReassignment.cpp for the def of isGPR


https://github.com/llvm/llvm-project/pull/98603