[llvm] [X86][RA] Add two address hints for compressible NDD instructions. (PR #98603)

[Shengchen Kan via llvm-commits]

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@@ -1082,8 +1088,46 @@ bool X86RegisterInfo::getRegAllocationHints(Register VirtReg,
       VirtReg, Order, Hints, MF, VRM, Matrix);
 
   unsigned ID = RC.getID();
-  if (ID != X86::TILERegClassID)
+
+  if (ID != X86::TILERegClassID) {
+    if (!VRM || DisableRegAllocNDDHints)
+      return BaseImplRetVal;
+
+    // Add any two address hints after any copy hints.
+    SmallSet<unsigned, 4> TwoAddrHints;
+
+    auto TryAddNDDHint = [&](const MachineOperand &MO) {
+      Register Reg = MO.getReg();
+      Register PhysReg =
+          Register::isPhysicalRegister(Reg) ? Reg : Register(VRM->getPhys(Reg));
+      if (PhysReg && !MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
+        TwoAddrHints.insert(PhysReg);
+    };
+
+    // NDD instructions is compressible when Op0 is allocated to the same
+    // physic register as Op1 (or Op2 is it's commutable).
+    for (auto &MO : MRI->reg_nodbg_operands(VirtReg)) {
+      const MachineInstr &MI = *MO.getParent();
+      if (X86::getNonNDVariant(MI.getOpcode()) == 0)
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KanRobert wrote:

Not possible. https://www.godbolt.org/z/jdaaes4rc

https://github.com/llvm/llvm-project/pull/98603