[llvm] 9bd97fc - [RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 27 17:26:35 PDT 2024
Author: Craig Topper
Date: 2024-07-27T17:26:32-07:00
New Revision: 9bd97fcf1385efea2dc130ee4fa78665fa6c9205
URL: https://github.com/llvm/llvm-project/commit/9bd97fcf1385efea2dc130ee4fa78665fa6c9205
DIFF: https://github.com/llvm/llvm-project/commit/9bd97fcf1385efea2dc130ee4fa78665fa6c9205.diff
LOG: [RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)
Ventana doesn't have RV32 cores so the instructions aren't really
supported for RV32, but there's nothing specifically 64-bit about them.
My goal here is to fix cannot select errors if XVentanaCondOps is
enabled on RV32. Alternatively, we could quality the lowering code to
also check IsRV64 so that we don't create RISCVISD::CZERO* nodes. Fixing
the isel patterns seemed simpler.
Fixes #100855.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
llvm/test/CodeGen/RISCV/condops.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
index d0a798ef475c4..b1a7a18a3bf85 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
@@ -14,7 +14,7 @@
// XVentanaCondOps
//===----------------------------------------------------------------------===//
-let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
+let Predicates = [HasVendorXVentanaCondOps], hasSideEffects = 0,
mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "XVentana" in
class VTMaskedMove<bits<3> funct3, string opcodestr>
: RVInstR<0b0000000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
@@ -28,18 +28,18 @@ def VT_MASKC : VTMaskedMove<0b110, "vt.maskc">,
def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-let Predicates = [IsRV64, HasVendorXVentanaCondOps] in {
-def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
+let Predicates = [HasVendorXVentanaCondOps] in {
+def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
(VT_MASKC GPR:$rs1, GPR:$rc)>;
-def : Pat<(i64 (riscv_czero_nez GPR:$rs1, GPR:$rc)),
+def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)),
(VT_MASKCN GPR:$rs1, GPR:$rc)>;
-def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, (riscv_setne (i64 GPR:$rc)))),
+def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
(VT_MASKC GPR:$rs1, GPR:$rc)>;
-def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, (riscv_seteq (i64 GPR:$rc)))),
+def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
(VT_MASKCN GPR:$rs1, GPR:$rc)>;
-def : Pat<(i64 (riscv_czero_nez GPR:$rs1, (riscv_setne (i64 GPR:$rc)))),
+def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
(VT_MASKCN GPR:$rs1, GPR:$rc)>;
-def : Pat<(i64 (riscv_czero_nez GPR:$rs1, (riscv_seteq (i64 GPR:$rc)))),
+def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
(VT_MASKC GPR:$rs1, GPR:$rc)>;
-} // Predicates = [IsRV64, HasVendorXVentanaCondOps]
+} // Predicates = [HasVendorXVentanaCondOps]
diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll
index 101cb5aeeb094..622365cf13bce 100644
--- a/llvm/test/CodeGen/RISCV/condops.ll
+++ b/llvm/test/CodeGen/RISCV/condops.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV32XVENTANACONDOPS
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS
; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV
; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND
@@ -20,6 +21,12 @@ define i64 @zero1(i64 %rs1, i1 zeroext %rc) {
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero1:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero1:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a1
@@ -58,6 +65,12 @@ define i64 @zero2(i64 %rs1, i1 zeroext %rc) {
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero2:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero2:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a1
@@ -98,6 +111,13 @@ define i64 @zero_singlebit1(i64 %rs1, i64 %rs2) {
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero_singlebit1:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: bexti a2, a2, 12
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero_singlebit1:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: bexti a1, a1, 12
@@ -145,6 +165,13 @@ define i64 @zero_singlebit2(i64 %rs1, i64 %rs2) {
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero_singlebit2:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: bexti a2, a2, 12
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero_singlebit2:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: bexti a1, a1, 12
@@ -195,6 +222,16 @@ define i64 @add1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: add1:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a4, a0
+; RV32XVENTANACONDOPS-NEXT: add a2, a2, a4
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a3, a0
+; RV32XVENTANACONDOPS-NEXT: add a0, a1, a0
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: add a1, a2, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: add1:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0
@@ -246,6 +283,16 @@ define i64 @add2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: add2:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0
+; RV32XVENTANACONDOPS-NEXT: add a2, a4, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0
+; RV32XVENTANACONDOPS-NEXT: add a0, a3, a0
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a0, a3
+; RV32XVENTANACONDOPS-NEXT: add a1, a2, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: add2:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0
@@ -297,6 +344,16 @@ define i64 @add3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: add3:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a0
+; RV32XVENTANACONDOPS-NEXT: add a2, a2, a4
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a3, a0
+; RV32XVENTANACONDOPS-NEXT: add a0, a1, a0
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: add a1, a2, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: add3:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0
@@ -348,6 +405,16 @@ define i64 @add4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: add4:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0
+; RV32XVENTANACONDOPS-NEXT: add a2, a4, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0
+; RV32XVENTANACONDOPS-NEXT: add a0, a3, a0
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a0, a3
+; RV32XVENTANACONDOPS-NEXT: add a1, a2, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: add4:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0
@@ -400,6 +467,17 @@ define i64 @sub1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: sub1:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0
+; RV32XVENTANACONDOPS-NEXT: sltu a5, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a0
+; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a0
+; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a5
+; RV32XVENTANACONDOPS-NEXT: sub a0, a1, a3
+; RV32XVENTANACONDOPS-NEXT: mv a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: sub1:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0
@@ -453,6 +531,17 @@ define i64 @sub2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: sub2:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0
+; RV32XVENTANACONDOPS-NEXT: sltu a5, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a0
+; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a0
+; RV32XVENTANACONDOPS-NEXT: sub a2, a2, a5
+; RV32XVENTANACONDOPS-NEXT: sub a0, a1, a3
+; RV32XVENTANACONDOPS-NEXT: mv a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: sub2:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0
@@ -503,6 +592,15 @@ define i64 @or1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: or1:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0
+; RV32XVENTANACONDOPS-NEXT: or a3, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a4, a0
+; RV32XVENTANACONDOPS-NEXT: or a1, a2, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: or1:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0
@@ -551,6 +649,15 @@ define i64 @or2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: or2:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0
+; RV32XVENTANACONDOPS-NEXT: or a3, a3, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a2, a0
+; RV32XVENTANACONDOPS-NEXT: or a1, a4, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: or2:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0
@@ -599,6 +706,15 @@ define i64 @or3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: or3:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0
+; RV32XVENTANACONDOPS-NEXT: or a3, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a4, a0
+; RV32XVENTANACONDOPS-NEXT: or a1, a2, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: or3:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0
@@ -647,6 +763,15 @@ define i64 @or4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: or4:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a0
+; RV32XVENTANACONDOPS-NEXT: or a3, a3, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a2, a0
+; RV32XVENTANACONDOPS-NEXT: or a1, a4, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: or4:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0
@@ -695,6 +820,15 @@ define i64 @xor1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: xor1:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0
+; RV32XVENTANACONDOPS-NEXT: xor a3, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a4, a0
+; RV32XVENTANACONDOPS-NEXT: xor a1, a2, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: xor1:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0
@@ -743,6 +877,15 @@ define i64 @xor2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: xor a0, a2, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: xor2:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0
+; RV32XVENTANACONDOPS-NEXT: xor a3, a3, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a2, a0
+; RV32XVENTANACONDOPS-NEXT: xor a1, a4, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: xor2:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0
@@ -791,6 +934,15 @@ define i64 @xor3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: xor3:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0
+; RV32XVENTANACONDOPS-NEXT: xor a3, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a4, a0
+; RV32XVENTANACONDOPS-NEXT: xor a1, a2, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: xor3:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0
@@ -839,6 +991,15 @@ define i64 @xor4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: xor a0, a2, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: xor4:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a0
+; RV32XVENTANACONDOPS-NEXT: xor a3, a3, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a2, a0
+; RV32XVENTANACONDOPS-NEXT: xor a1, a4, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: xor4:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0
@@ -891,6 +1052,17 @@ define i64 @and1(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: and1:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: and a4, a2, a4
+; RV32XVENTANACONDOPS-NEXT: and a3, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a0
+; RV32XVENTANACONDOPS-NEXT: or a3, a3, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a2, a0
+; RV32XVENTANACONDOPS-NEXT: or a1, a4, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: and1:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: and a2, a1, a2
@@ -948,6 +1120,17 @@ define i64 @and2(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: and2:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: and a5, a2, a4
+; RV32XVENTANACONDOPS-NEXT: and a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a3, a0
+; RV32XVENTANACONDOPS-NEXT: or a2, a1, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a4, a0
+; RV32XVENTANACONDOPS-NEXT: or a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: and2:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: and a1, a1, a2
@@ -1005,6 +1188,17 @@ define i64 @and3(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: and3:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: and a4, a2, a4
+; RV32XVENTANACONDOPS-NEXT: and a3, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0
+; RV32XVENTANACONDOPS-NEXT: or a3, a3, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a2, a0
+; RV32XVENTANACONDOPS-NEXT: or a1, a4, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: and3:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: and a2, a1, a2
@@ -1062,6 +1256,17 @@ define i64 @and4(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: and4:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: and a5, a2, a4
+; RV32XVENTANACONDOPS-NEXT: and a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a3, a0
+; RV32XVENTANACONDOPS-NEXT: or a2, a1, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a4, a0
+; RV32XVENTANACONDOPS-NEXT: or a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: and4:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: and a1, a1, a2
@@ -1119,6 +1324,17 @@ define i64 @basic(i1 zeroext %rc, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: basic:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0
+; RV32XVENTANACONDOPS-NEXT: or a3, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a4, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: mv a0, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: basic:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0
@@ -1177,6 +1393,19 @@ define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: seteq:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a6, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a7, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: seteq:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1
@@ -1241,6 +1470,19 @@ define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setne:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a6, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a7, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setne:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1
@@ -1309,6 +1551,22 @@ define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setgt:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
+; RV32XVENTANACONDOPS-NEXT: slt a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a6, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a7, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setgt:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: slt a0, a1, a0
@@ -1380,6 +1638,22 @@ define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setge:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
+; RV32XVENTANACONDOPS-NEXT: slt a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a6, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a7, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setge:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: slt a0, a0, a1
@@ -1451,6 +1725,22 @@ define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setlt:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
+; RV32XVENTANACONDOPS-NEXT: slt a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a6, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a7, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setlt:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: slt a0, a0, a1
@@ -1522,6 +1812,22 @@ define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setle:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
+; RV32XVENTANACONDOPS-NEXT: slt a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a6, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a7, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setle:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: slt a0, a1, a0
@@ -1593,6 +1899,22 @@ define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setugt:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a6, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a7, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setugt:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: sltu a0, a1, a0
@@ -1664,6 +1986,22 @@ define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setuge:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a6, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a7, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setuge:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: sltu a0, a0, a1
@@ -1735,6 +2073,22 @@ define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setult:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a6, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a7, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setult:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: sltu a0, a0, a1
@@ -1806,6 +2160,22 @@ define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setule:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor t0, a1, a3
+; RV32XVENTANACONDOPS-NEXT: sltu a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0
+; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a6, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a7, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setule:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: sltu a0, a1, a0
@@ -1871,6 +2241,17 @@ define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: seteq_zero:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a5, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: seteq_zero:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0
@@ -1928,6 +2309,17 @@ define i64 @setne_zero(i64 %a, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setne_zero:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a5, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setne_zero:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0
@@ -1987,6 +2379,18 @@ define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: seteq_constant:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 123
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a5, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: seteq_constant:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -123
@@ -2050,6 +2454,18 @@ define i64 @setne_constant(i64 %a, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setne_constant:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 456
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a5, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setne_constant:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -456
@@ -2113,6 +2529,18 @@ define i64 @seteq_2048(i64 %a, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: seteq_2048:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: binvi a0, a0, 11
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a5, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: seteq_2048:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -2048
@@ -2177,6 +2605,19 @@ define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: seteq_neg2048:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: not a1, a1
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a5, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: seteq_neg2048:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048
@@ -2242,6 +2683,19 @@ define i64 @setne_neg2048(i64 %a, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setne_neg2048:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: not a1, a1
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a1
+; RV32XVENTANACONDOPS-NEXT: or a0, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a5, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setne_neg2048:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048
@@ -2302,6 +2756,15 @@ define i64 @zero1_seteq(i64 %a, i64 %b, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero1_seteq:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero1_seteq:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1
@@ -2354,6 +2817,15 @@ define i64 @zero2_seteq(i64 %a, i64 %b, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero2_seteq:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero2_seteq:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1
@@ -2406,6 +2878,15 @@ define i64 @zero1_setne(i64 %a, i64 %b, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero1_setne:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a4, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero1_setne:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1
@@ -2458,6 +2939,15 @@ define i64 @zero2_setne(i64 %a, i64 %b, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero2_setne:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xor a1, a1, a3
+; RV32XVENTANACONDOPS-NEXT: xor a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a4, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a5, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero2_setne:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1
@@ -2507,6 +2997,13 @@ define i64 @zero1_seteq_zero(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero1_seteq_zero:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero1_seteq_zero:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0
@@ -2551,6 +3048,13 @@ define i64 @zero2_seteq_zero(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero2_seteq_zero:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero2_seteq_zero:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0
@@ -2595,6 +3099,13 @@ define i64 @zero1_setne_zero(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero1_setne_zero:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero1_setne_zero:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0
@@ -2639,6 +3150,13 @@ define i64 @zero2_setne_zero(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero2_setne_zero:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero2_setne_zero:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0
@@ -2686,6 +3204,15 @@ define i64 @zero1_seteq_constant(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero1_seteq_constant:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: not a1, a1
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -231
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero1_seteq_constant:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: addi a0, a0, 231
@@ -2737,6 +3264,14 @@ define i64 @zero2_seteq_constant(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero2_seteq_constant:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 546
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero2_seteq_constant:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -546
@@ -2787,6 +3322,14 @@ define i64 @zero1_setne_constant(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero1_setne_constant:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, 321
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero1_setne_constant:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -321
@@ -2838,6 +3381,15 @@ define i64 @zero2_setne_constant(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero2_setne_constant:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: not a1, a1
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -654
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero2_setne_constant:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: addi a0, a0, 654
@@ -2890,6 +3442,15 @@ define i64 @zero1_seteq_neg2048(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero1_seteq_neg2048:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: not a1, a1
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero1_seteq_neg2048:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048
@@ -2942,6 +3503,15 @@ define i64 @zero2_seteq_neg2048(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero2_seteq_neg2048:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: not a1, a1
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero2_seteq_neg2048:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048
@@ -2994,6 +3564,15 @@ define i64 @zero1_setne_neg2048(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero1_setne_neg2048:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: not a1, a1
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero1_setne_neg2048:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048
@@ -3046,6 +3625,15 @@ define i64 @zero2_setne_neg2048(i64 %a, i64 %rs1) {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: zero2_setne_neg2048:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: not a1, a1
+; RV32XVENTANACONDOPS-NEXT: xori a0, a0, -2048
+; RV32XVENTANACONDOPS-NEXT: or a1, a0, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: zero2_setne_neg2048:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048
@@ -3125,6 +3713,28 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: sextw_removal_maskc:
+; RV32XVENTANACONDOPS: # %bb.0: # %bb
+; RV32XVENTANACONDOPS-NEXT: addi sp, sp, -16
+; RV32XVENTANACONDOPS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32XVENTANACONDOPS-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32XVENTANACONDOPS-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32XVENTANACONDOPS-NEXT: mv s0, a2
+; RV32XVENTANACONDOPS-NEXT: andi a0, a0, 1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc s1, a1, a0
+; RV32XVENTANACONDOPS-NEXT: .LBB56_1: # %bb2
+; RV32XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32XVENTANACONDOPS-NEXT: mv a0, s1
+; RV32XVENTANACONDOPS-NEXT: call bar
+; RV32XVENTANACONDOPS-NEXT: sll s1, s1, s0
+; RV32XVENTANACONDOPS-NEXT: bnez a0, .LBB56_1
+; RV32XVENTANACONDOPS-NEXT: # %bb.2: # %bb7
+; RV32XVENTANACONDOPS-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32XVENTANACONDOPS-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32XVENTANACONDOPS-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32XVENTANACONDOPS-NEXT: addi sp, sp, 16
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: sextw_removal_maskc:
; RV64XVENTANACONDOPS: # %bb.0: # %bb
; RV64XVENTANACONDOPS-NEXT: addi sp, sp, -32
@@ -3276,6 +3886,28 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: sextw_removal_maskcn:
+; RV32XVENTANACONDOPS: # %bb.0: # %bb
+; RV32XVENTANACONDOPS-NEXT: addi sp, sp, -16
+; RV32XVENTANACONDOPS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32XVENTANACONDOPS-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32XVENTANACONDOPS-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32XVENTANACONDOPS-NEXT: mv s0, a2
+; RV32XVENTANACONDOPS-NEXT: andi a0, a0, 1
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn s1, a1, a0
+; RV32XVENTANACONDOPS-NEXT: .LBB57_1: # %bb2
+; RV32XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32XVENTANACONDOPS-NEXT: mv a0, s1
+; RV32XVENTANACONDOPS-NEXT: call bar
+; RV32XVENTANACONDOPS-NEXT: sll s1, s1, s0
+; RV32XVENTANACONDOPS-NEXT: bnez a0, .LBB57_1
+; RV32XVENTANACONDOPS-NEXT: # %bb.2: # %bb7
+; RV32XVENTANACONDOPS-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32XVENTANACONDOPS-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32XVENTANACONDOPS-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32XVENTANACONDOPS-NEXT: addi sp, sp, 16
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: sextw_removal_maskcn:
; RV64XVENTANACONDOPS: # %bb.0: # %bb
; RV64XVENTANACONDOPS-NEXT: addi sp, sp, -32
@@ -3398,6 +4030,14 @@ define i32 @setune_32(float %a, float %b, i32 %rs1, i32 %rs2) {
; RV64I-NEXT: .LBB58_2:
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setune_32:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setune_32:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa1
@@ -3452,6 +4092,17 @@ define i64 @setune_64(float %a, float %b, i64 %rs1, i64 %rs2) {
; RV64I-NEXT: .LBB59_2:
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: setune_64:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: feq.s a4, fa0, fa1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a4
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a4
+; RV32XVENTANACONDOPS-NEXT: or a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a3, a4
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a4
+; RV32XVENTANACONDOPS-NEXT: or a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: setune_64:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa1
@@ -3534,6 +4185,25 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: numsignbits:
+; RV32XVENTANACONDOPS: # %bb.0:
+; RV32XVENTANACONDOPS-NEXT: addi sp, sp, -16
+; RV32XVENTANACONDOPS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32XVENTANACONDOPS-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0
+; RV32XVENTANACONDOPS-NEXT: vt.maskcn s0, a3, a0
+; RV32XVENTANACONDOPS-NEXT: or s0, s0, a2
+; RV32XVENTANACONDOPS-NEXT: beqz a1, .LBB60_2
+; RV32XVENTANACONDOPS-NEXT: # %bb.1:
+; RV32XVENTANACONDOPS-NEXT: mv a0, s0
+; RV32XVENTANACONDOPS-NEXT: call bat
+; RV32XVENTANACONDOPS-NEXT: .LBB60_2:
+; RV32XVENTANACONDOPS-NEXT: mv a0, s0
+; RV32XVENTANACONDOPS-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32XVENTANACONDOPS-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32XVENTANACONDOPS-NEXT: addi sp, sp, 16
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: numsignbits:
; RV64XVENTANACONDOPS: # %bb.0:
; RV64XVENTANACONDOPS-NEXT: addi sp, sp, -16
@@ -3639,6 +4309,13 @@ define i64 @single_bit(i64 %x) {
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: single_bit:
+; RV32XVENTANACONDOPS: # %bb.0: # %entry
+; RV32XVENTANACONDOPS-NEXT: andi a2, a0, 1024
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: single_bit:
; RV64XVENTANACONDOPS: # %bb.0: # %entry
; RV64XVENTANACONDOPS-NEXT: andi a1, a0, 1024
@@ -3688,6 +4365,13 @@ define i64 @single_bit2(i64 %x) {
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: single_bit2:
+; RV32XVENTANACONDOPS: # %bb.0: # %entry
+; RV32XVENTANACONDOPS-NEXT: bexti a2, a0, 11
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a0, a2
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: single_bit2:
; RV64XVENTANACONDOPS: # %bb.0: # %entry
; RV64XVENTANACONDOPS-NEXT: bexti a1, a0, 11
@@ -3738,6 +4422,14 @@ define i64 @single_bit3(i80 %x, i64 %y) {
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: ret
;
+; RV32XVENTANACONDOPS-LABEL: single_bit3:
+; RV32XVENTANACONDOPS: # %bb.0: # %entry
+; RV32XVENTANACONDOPS-NEXT: lw a0, 8(a0)
+; RV32XVENTANACONDOPS-NEXT: andi a3, a0, 1
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a3
+; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a2, a3
+; RV32XVENTANACONDOPS-NEXT: ret
+;
; RV64XVENTANACONDOPS-LABEL: single_bit3:
; RV64XVENTANACONDOPS: # %bb.0: # %entry
; RV64XVENTANACONDOPS-NEXT: andi a1, a1, 1
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