[llvm] [AsmPrinter] Don't EmitToStreamer instructions lowered by tblgenned code (PR #100803)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 26 12:27:36 PDT 2024
https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/100803
This allows lowering individual instructions in a bundle before a single call to EmitToStreamer for VLIW targets.
>From 60f3e10d96f3c8ba18ac9caa0ee30db86dd7d239 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Fri, 26 Jul 2024 22:23:47 +0300
Subject: [PATCH] [AsmPrinter] Don't EmitToStreamer instructions lowered by
tblgenned code
This allows lowering individual instructions in a bundle
before a single call to EmitToStreamer for VLIW targets.
---
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 7 +++---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h | 3 +--
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp | 6 +++--
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 4 +++-
llvm/lib/Target/ARM/ARMAsmPrinter.h | 5 ++--
llvm/lib/Target/ARM/ARMMCInstLower.cpp | 2 +-
llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp | 4 +++-
llvm/lib/Target/CSKY/CSKYAsmPrinter.h | 3 +--
.../Target/LoongArch/LoongArchAsmPrinter.cpp | 4 +++-
.../Target/LoongArch/LoongArchAsmPrinter.h | 4 ++--
llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 4 +++-
llvm/lib/Target/Mips/MipsAsmPrinter.h | 3 +--
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 9 +++----
llvm/utils/TableGen/PseudoLoweringEmitter.cpp | 24 +++++++++----------
14 files changed, 44 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 3c9b07ad45bf2..320de1e3dfb5d 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -160,8 +160,7 @@ class AArch64AsmPrinter : public AsmPrinter {
/// tblgen'erated driver function for lowering simple MI->MC
/// pseudo instructions.
- bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
- const MachineInstr *MI);
+ bool lowerMachineInstrToMCInstImpl(const MachineInstr *MI, MCInst &Inst);
void emitInstruction(const MachineInstr *MI) override;
@@ -2316,8 +2315,10 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
AArch64_MC::verifyInstructionPredicates(MI->getOpcode(), STI->getFeatureBits());
// Do any auto-generated pseudo lowerings.
- if (emitPseudoExpansionLowering(*OutStreamer, MI))
+ if (MCInst OutInst; lowerMachineInstrToMCInstImpl(MI, OutInst)) {
+ EmitToStreamer(*OutStreamer, OutInst);
return;
+ }
if (MI->getOpcode() == AArch64::ADRP) {
for (auto &Opd : MI->operands()) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
index f70a60aef0073..5c8851d58656b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h
@@ -109,8 +109,7 @@ class AMDGPUAsmPrinter final : public AsmPrinter {
/// tblgen'erated driver function for lowering simple MI->MC pseudo
/// instructions.
- bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
- const MachineInstr *MI);
+ bool lowerMachineInstrToMCInstImpl(const MachineInstr *MI, MCInst &Inst);
/// Implemented in AMDGPUMCInstLower.cpp
void emitInstruction(const MachineInstr *MI) override;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
index 45ec38cfb4dbc..9dab7f55bc9ab 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -118,7 +118,7 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
unsigned Opcode = MI->getOpcode();
const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
- // FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
+ // FIXME: Should be able to handle this with lowerMachineInstrToMCInstImpl. We
// need to select it to the subtarget specific version, and there's no way to
// do that with a single pseudo source operation.
if (Opcode == AMDGPU::S_SETPC_B64_return)
@@ -187,8 +187,10 @@ void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) {
// AMDGPU_MC::verifyInstructionPredicates(MI->getOpcode(),
// getSubtargetInfo().getFeatureBits());
- if (emitPseudoExpansionLowering(*OutStreamer, MI))
+ if (MCInst OutInst; lowerMachineInstrToMCInstImpl(MI, OutInst)) {
+ EmitToStreamer(*OutStreamer, OutInst);
return;
+ }
const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 642739a29d6b0..b558e4e00c91a 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1447,8 +1447,10 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
EmitUnwindingInstruction(MI);
// Do any auto-generated pseudo lowerings.
- if (emitPseudoExpansionLowering(*OutStreamer, MI))
+ if (MCInst OutInst; lowerMachineInstrToMCInstImpl(MI, OutInst)) {
+ EmitToStreamer(*OutStreamer, OutInst);
return;
+ }
assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
"Pseudo flag setting opcode should be expanded early");
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.h b/llvm/lib/Target/ARM/ARMAsmPrinter.h
index 33b4417aa9b80..e399b23ac19f0 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.h
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.h
@@ -126,9 +126,8 @@ class LLVM_LIBRARY_VISIBILITY ARMAsmPrinter : public AsmPrinter {
void EmitUnwindingInstruction(const MachineInstr *MI);
- // emitPseudoExpansionLowering - tblgen'erated.
- bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
- const MachineInstr *MI);
+ // tblgen'erated.
+ bool lowerMachineInstrToMCInstImpl(const MachineInstr *MI, MCInst &Inst);
public:
unsigned getISAEncoding() override {
diff --git a/llvm/lib/Target/ARM/ARMMCInstLower.cpp b/llvm/lib/Target/ARM/ARMMCInstLower.cpp
index 2c2853223ba56..ec1f2bcc1614b 100644
--- a/llvm/lib/Target/ARM/ARMMCInstLower.cpp
+++ b/llvm/lib/Target/ARM/ARMMCInstLower.cpp
@@ -218,7 +218,7 @@ void ARMAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
// Emit "B #20" instruction, which jumps over the next 24 bytes (because
// register pc is 8 bytes ahead of the jump instruction by the moment CPU
// is executing it).
- // By analogy to ARMAsmPrinter::emitPseudoExpansionLowering() |case ARM::B|.
+ // By analogy to ARMAsmPrinter::lowerMachineInstrToMCInstImpl() |case ARM::B|.
// It is not clear why |addReg(0)| is needed (the last operand).
EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc).addImm(20)
.addImm(ARMCC::AL).addReg(0));
diff --git a/llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp b/llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp
index 7d121b8d24f05..4d3754b6d47c5 100644
--- a/llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp
+++ b/llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp
@@ -145,8 +145,10 @@ void CSKYAsmPrinter::emitInstruction(const MachineInstr *MI) {
getSubtargetInfo().getFeatureBits());
// Do any auto-generated pseudo lowerings.
- if (emitPseudoExpansionLowering(*OutStreamer, MI))
+ if (MCInst OutInst; lowerMachineInstrToMCInstImpl(MI, OutInst)) {
+ EmitToStreamer(*OutStreamer, OutInst);
return;
+ }
// If we just ended a constant pool, mark it as such.
if (InConstantPool && MI->getOpcode() != CSKY::CONSTPOOL_ENTRY) {
diff --git a/llvm/lib/Target/CSKY/CSKYAsmPrinter.h b/llvm/lib/Target/CSKY/CSKYAsmPrinter.h
index 379189512405a..64f7178e72d20 100644
--- a/llvm/lib/Target/CSKY/CSKYAsmPrinter.h
+++ b/llvm/lib/Target/CSKY/CSKYAsmPrinter.h
@@ -41,8 +41,7 @@ class LLVM_LIBRARY_VISIBILITY CSKYAsmPrinter : public AsmPrinter {
/// tblgen'erated driver function for lowering simple MI->MC
/// pseudo instructions.
- bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
- const MachineInstr *MI);
+ bool lowerMachineInstrToMCInstImpl(const MachineInstr *MI, MCInst &Inst);
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override;
diff --git a/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp b/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
index 27979a830b10e..f977b1a41d1f0 100644
--- a/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.cpp
@@ -34,8 +34,10 @@ void LoongArchAsmPrinter::emitInstruction(const MachineInstr *MI) {
MI->getOpcode(), getSubtargetInfo().getFeatureBits());
// Do any auto-generated pseudo lowerings.
- if (emitPseudoExpansionLowering(*OutStreamer, MI))
+ if (MCInst OutInst; lowerMachineInstrToMCInstImpl(MI, OutInst)) {
+ EmitToStreamer(*OutStreamer, OutInst);
return;
+ }
switch (MI->getOpcode()) {
case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
diff --git a/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h b/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
index 693456443c7a4..11510ef28dc5f 100644
--- a/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
+++ b/llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h
@@ -47,8 +47,8 @@ class LLVM_LIBRARY_VISIBILITY LoongArchAsmPrinter : public AsmPrinter {
void emitSled(const MachineInstr &MI, SledKind Kind);
// tblgen'erated function.
- bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
- const MachineInstr *MI);
+ bool lowerMachineInstrToMCInstImpl(const MachineInstr *MI, MCInst &Inst);
+
// Wrapper needed for tblgenned pseudo lowering.
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
return lowerLoongArchMachineOperandToMCOperand(MO, MCOp, *this);
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index 018c620f5c84c..6f64676dac59e 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -254,8 +254,10 @@ void MipsAsmPrinter::emitInstruction(const MachineInstr *MI) {
do {
// Do any auto-generated pseudo lowerings.
- if (emitPseudoExpansionLowering(*OutStreamer, &*I))
+ if (MCInst OutInst; lowerMachineInstrToMCInstImpl(&*I, OutInst)) {
+ EmitToStreamer(*OutStreamer, OutInst);
continue;
+ }
// Skip the BUNDLE pseudo instruction and lower the contents
if (I->isBundle())
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.h b/llvm/lib/Target/Mips/MipsAsmPrinter.h
index 0b55089385d79..6de4bc67c388d 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.h
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.h
@@ -69,8 +69,7 @@ class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter {
void EmitSled(const MachineInstr &MI, SledKind Kind);
// tblgen'erated function.
- bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
- const MachineInstr *MI);
+ bool lowerMachineInstrToMCInstImpl(const MachineInstr *MI, MCInst &Inst);
// Emit PseudoReturn, PseudoReturn64, PseudoIndirectBranch,
// and PseudoIndirectBranch64 as a JR, JR_MM, JALR, or JALR64 as appropriate
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index c0a4d0e9c520f..407a34be25881 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -84,8 +84,8 @@ class RISCVAsmPrinter : public AsmPrinter {
// Returns whether Inst is compressed.
bool EmitToStreamer(MCStreamer &S, const MCInst &Inst);
- bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
- const MachineInstr *MI);
+
+ bool lowerMachineInstrToMCInstImpl(const MachineInstr *MI, MCInst &Inst);
typedef std::tuple<unsigned, uint32_t> HwasanMemaccessTuple;
std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
@@ -291,9 +291,10 @@ void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
emitNTLHint(MI);
// Do any auto-generated pseudo lowerings.
- if (emitPseudoExpansionLowering(*OutStreamer, MI))
+ if (MCInst OutInst; lowerMachineInstrToMCInstImpl(MI, OutInst)) {
+ EmitToStreamer(*OutStreamer, OutInst);
return;
-
+ }
switch (MI->getOpcode()) {
case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
diff --git a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
index 01cfd4a1d9829..ec25b2ca72959 100644
--- a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
+++ b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
@@ -227,22 +227,21 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
// Emit file header.
emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
- o << "bool " << Target.getName() + "AsmPrinter"
- << "::\n"
- << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
- << " const MachineInstr *MI) {\n";
+ o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
+ << "lowerMachineInstrToMCInstImpl(const MachineInstr *MI, MCInst &Inst) "
+ "{\n";
if (!Expansions.empty()) {
- o << " switch (MI->getOpcode()) {\n"
+ o << " Inst.clear();\n"
+ << " switch (MI->getOpcode()) {\n"
<< " default: return false;\n";
for (auto &Expansion : Expansions) {
CodeGenInstruction &Source = Expansion.Source;
CodeGenInstruction &Dest = Expansion.Dest;
o << " case " << Source.Namespace << "::" << Source.TheDef->getName()
<< ": {\n"
- << " MCInst TmpInst;\n"
<< " MCOperand MCOp;\n"
- << " TmpInst.setOpcode(" << Dest.Namespace
+ << " Inst.setOpcode(" << Dest.Namespace
<< "::" << Dest.TheDef->getName() << ");\n";
// Copy the operands from the source instruction.
@@ -260,15 +259,15 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
.MIOperandNo +
i
<< "), MCOp);\n"
- << " TmpInst.addOperand(MCOp);\n";
+ << " Inst.addOperand(MCOp);\n";
break;
case OpData::Imm:
- o << " TmpInst.addOperand(MCOperand::createImm("
+ o << " Inst.addOperand(MCOperand::createImm("
<< Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
break;
case OpData::Reg: {
Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
- o << " TmpInst.addOperand(MCOperand::createReg(";
+ o << " Inst.addOperand(MCOperand::createReg(";
// "zero_reg" is special.
if (Reg->getName() == "zero_reg")
o << "0";
@@ -287,10 +286,9 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
o << " for (unsigned i = " << MIOpNo
<< ", e = MI->getNumOperands(); i != e; ++i)\n"
<< " if (lowerOperand(MI->getOperand(i), MCOp))\n"
- << " TmpInst.addOperand(MCOp);\n";
+ << " Inst.addOperand(MCOp);\n";
}
- o << " EmitToStreamer(OutStreamer, TmpInst);\n"
- << " break;\n"
+ o << " break;\n"
<< " }\n";
}
o << " }\n return true;";
More information about the llvm-commits
mailing list