[llvm] [RISCV][TTI] Properly model odd vector sized LD/ST operations (PR #100436)

[Philip Reames via llvm-commits]

================
@@ -1390,14 +1390,34 @@ InstructionCost RISCVTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
   InstructionCost Cost = 0;
   if (Opcode == Instruction::Store && OpInfo.isConstant())
     Cost += getStoreImmCost(Src, OpInfo, CostKind);
-  InstructionCost BaseCost =
-    BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
-                           CostKind, OpInfo, I);
+
+  std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Src);
+
+  InstructionCost BaseCost = [&]() {
+    InstructionCost Cost = LT.first;
+    if (CostKind != TTI::TCK_RecipThroughput)
+      return Cost;
+
+    // Our actual lowering uses a VL predicated load of the next legal type,
+    // or splitting if there is no wider legal type.  This is reflected in
+    // the result of getTypeLegalizationCost, but BasicTTI assumes the
+    // widened cases are scalarized.
+    const DataLayout &DL = this->getDataLayout();
+    if (Src->isVectorTy() && LT.second.isVector()) {
+      auto *SrcVT = cast<VectorType>(Src);
+      TypeSize SrcEltSize = DL.getTypeStoreSizeInBits(SrcVT->getElementType());
+      TypeSize LegalEltSize = LT.second.getVectorElementType().getSizeInBits();
+      if (SrcEltSize == LegalEltSize)
----------------
preames wrote:

Thanks for pushing on this.  I went back and ran the local tests with the assert, and found out that my assert/check was actually entirely spurious.  

The case that I found locally (without the isKnownLE check) is:
```
<2 x i1> 
v2i1 
```

After staring at that for a moment, and going "huh?", I realized that the check was using the Store size of the element from DL, and the non-store width of the element from the VT.  Fixing that mismatch causes the assert to never fail.  

Given that, I'm just going to remove the check entirely.  



https://github.com/llvm/llvm-project/pull/100436