[llvm] [Xtensa] Implement lowering Mul/Div/Shift operations. (PR #99981)

[Sergei Barannikov via llvm-commits]

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@@ -40,6 +40,10 @@ enum {
   // the lhs and rhs (ops #0 and #1) of a conditional expression with the
   // condition code in op #4
   SELECT_CC,
+
+  // Shift
+  SRCL,
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s-barannikov wrote:

How are these different from ISD opcodes? They deserve a comment.


https://github.com/llvm/llvm-project/pull/99981