[llvm] [AMDGPU] Always lower s/udiv64 by constant to MUL (PR #100723)

[Pierre van Houtryve via llvm-commits]

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@@ -6405,7 +6405,8 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
     if (VT.isVector())
       WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
                                 VT.getVectorElementCount());
-    if (isOperationLegalOrCustom(ISD::MUL, WideVT)) {
+    if (isOperationLegalOrCustom(ISD::MUL, WideVT) ||
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Pierre-vh wrote:

I see, that makes sense.
I think I'll need to dive a bit into the RISCV backend to see why it's so prone to crashing on this.

The heuristics also needs a bit more thought put into it. I feel like we shouldn't blindly apply this combine, but it should also not rely on legality too much otherwise it won't kick in for AMDGPU

https://github.com/llvm/llvm-project/pull/100723