[llvm] AMDGPU/GlobalISel: Use getSubRegFromChannel (PR #100732)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 26 05:06:39 PDT 2024
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/100732
None
>From 555190247b3088d5c0a798d72f96633a90989bdd Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sun, 9 Aug 2020 15:34:31 -0400
Subject: [PATCH] AMDGPU/GlobalISel: Use getSubRegFromChannel
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 26 +++----------------
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 63048c7d1a0a1..aaa292291334c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -2169,27 +2169,6 @@ bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
return Ret;
}
-static int sizeToSubRegIndex(unsigned Size) {
- switch (Size) {
- case 32:
- return AMDGPU::sub0;
- case 64:
- return AMDGPU::sub0_sub1;
- case 96:
- return AMDGPU::sub0_sub1_sub2;
- case 128:
- return AMDGPU::sub0_sub1_sub2_sub3;
- case 256:
- return AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
- default:
- if (Size < 32)
- return AMDGPU::sub0;
- if (Size > 256)
- return -1;
- return sizeToSubRegIndex(llvm::bit_ceil(Size));
- }
-}
-
bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
Register DstReg = I.getOperand(0).getReg();
Register SrcReg = I.getOperand(1).getReg();
@@ -2293,8 +2272,9 @@ bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
return false;
if (SrcSize > 32) {
- int SubRegIdx = sizeToSubRegIndex(DstSize);
- if (SubRegIdx == -1)
+ unsigned SubRegIdx =
+ DstSize < 32 ? AMDGPU::sub0 : TRI.getSubRegFromChannel(0, DstSize / 32);
+ if (SubRegIdx == AMDGPU::NoSubRegister)
return false;
// Deal with weird cases where the class only partially supports the subreg
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