[llvm] [AMDGPU] Always lower s/udiv64 by constant to MUL (PR #100723)

[Pierre van Houtryve via llvm-commits]

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@@ -6405,7 +6405,8 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
     if (VT.isVector())
       WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
                                 VT.getVectorElementCount());
-    if (isOperationLegalOrCustom(ISD::MUL, WideVT)) {
+    if (isOperationLegalOrCustom(ISD::MUL, WideVT) ||
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Pierre-vh wrote:

I tried enabling it for all targets but it doesn't seem to always be profitable. At minimum we need a isTypeLegal check otherwise some targets even crash (riscv32).

I'll have another look

https://github.com/llvm/llvm-project/pull/100723