[llvm] [DAG] Support saturated truncate (PR #99418)

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git-clang-format --diff f8006a5932b1ccdf3a1eed7b20b5cb608c0a020c e840baec19387e935188215cc2c3e76e22b9e118 --extensions h,cpp -- llvm/include/llvm/CodeGen/ISDOpcodes.h llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp llvm/lib/CodeGen/TargetLoweringBase.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.h llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e6953ed67c..c42dc9d4fc 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1410,7 +1410,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     }
   }
 
-  for (MVT VT : { MVT::v8i16, MVT::v4i32 }) {
+  for (MVT VT : {MVT::v8i16, MVT::v4i32}) {
     setOperationAction(ISD::TRUNCATE_SSAT_S, VT, Custom);
     setOperationAction(ISD::TRUNCATE_SSAT_U, VT, Custom);
     setOperationAction(ISD::TRUNCATE_USAT_U, VT, Custom);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ead79ec47b..704caeab90 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8298,8 +8298,7 @@ SDValue RISCVTargetLowering::lowerVectorTruncLike(SDValue Op,
   do {
     SrcEltVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits() / 2);
     MVT ResultVT = ContainerVT.changeVectorElementType(SrcEltVT);
-    Result = DAG.getNode(NewOpc, DL, ResultVT, Result,
-                         Mask, VL);
+    Result = DAG.getNode(NewOpc, DL, ResultVT, Result, Mask, VL);
   } while (SrcEltVT != DstEltVT);
 
   if (SrcVT.isFixedLengthVector())

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https://github.com/llvm/llvm-project/pull/99418