[lld] [ELF] Support relocatable files using CREL (PR #98115)
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 25 09:44:19 PDT 2024
https://github.com/MaskRay updated https://github.com/llvm/llvm-project/pull/98115
>From 7f7f5d7ec9304c2b365b03c27d91bdf81dc543e9 Mon Sep 17 00:00:00 2001
From: Fangrui Song <i at maskray.me>
Date: Mon, 8 Jul 2024 23:13:23 -0700
Subject: [PATCH] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20initia?=
=?UTF-8?q?l=20version?=
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Created using spr 1.3.5-bogner
---
lld/ELF/DWARF.cpp | 3 +-
lld/ELF/ICF.cpp | 26 +++---
lld/ELF/InputFiles.cpp | 1 +
lld/ELF/InputFiles.h | 1 +
lld/ELF/InputSection.cpp | 73 ++++++++++++----
lld/ELF/InputSection.h | 14 +--
lld/ELF/LinkerScript.cpp | 2 +
lld/ELF/MarkLive.cpp | 11 ++-
lld/ELF/OutputSections.cpp | 136 ++++++++++++++++++++++++++++-
lld/ELF/OutputSections.h | 6 ++
lld/ELF/Relocations.cpp | 82 +++++++++--------
lld/ELF/Relocations.h | 99 ++++++++++++++++++++-
lld/ELF/SyntheticSections.cpp | 12 ++-
lld/ELF/SyntheticSections.h | 2 +-
lld/ELF/Writer.cpp | 13 ++-
lld/test/ELF/crel-rel-mixed.s | 22 +++++
lld/test/ELF/crel.s | 81 +++++++++++++++++
lld/test/ELF/debug-names.s | 2 +-
lld/test/ELF/gc-sections.s | 4 +
lld/test/ELF/icf1.s | 3 +
lld/test/ELF/icf4.s | 2 +-
lld/test/ELF/relocatable-crel-32.s | 71 +++++++++++++++
lld/test/ELF/relocatable-crel.s | 107 +++++++++++++++++++++++
23 files changed, 688 insertions(+), 85 deletions(-)
create mode 100644 lld/test/ELF/crel-rel-mixed.s
create mode 100644 lld/test/ELF/crel.s
create mode 100644 lld/test/ELF/relocatable-crel-32.s
create mode 100644 lld/test/ELF/relocatable-crel.s
diff --git a/lld/ELF/DWARF.cpp b/lld/ELF/DWARF.cpp
index 5d58e0c60a952..517d26810a378 100644
--- a/lld/ELF/DWARF.cpp
+++ b/lld/ELF/DWARF.cpp
@@ -136,7 +136,8 @@ template <class ELFT>
std::optional<RelocAddrEntry>
LLDDwarfObj<ELFT>::find(const llvm::DWARFSection &s, uint64_t pos) const {
auto &sec = static_cast<const LLDDWARFSection &>(s);
- const RelsOrRelas<ELFT> rels = sec.sec->template relsOrRelas<ELFT>();
+ const RelsOrRelas<ELFT> rels =
+ sec.sec->template relsOrRelas<ELFT>(/*supportsCrel=*/false);
if (rels.areRelocsRel())
return findAux(*sec.sec, pos, rels.rels);
return findAux(*sec.sec, pos, rels.relas);
diff --git a/lld/ELF/ICF.cpp b/lld/ELF/ICF.cpp
index bfc605c793a92..44e8a71cc6286 100644
--- a/lld/ELF/ICF.cpp
+++ b/lld/ELF/ICF.cpp
@@ -103,12 +103,12 @@ template <class ELFT> class ICF {
void segregate(size_t begin, size_t end, uint32_t eqClassBase, bool constant);
template <class RelTy>
- bool constantEq(const InputSection *a, ArrayRef<RelTy> relsA,
- const InputSection *b, ArrayRef<RelTy> relsB);
+ bool constantEq(const InputSection *a, Relocs<RelTy> relsA,
+ const InputSection *b, Relocs<RelTy> relsB);
template <class RelTy>
- bool variableEq(const InputSection *a, ArrayRef<RelTy> relsA,
- const InputSection *b, ArrayRef<RelTy> relsB);
+ bool variableEq(const InputSection *a, Relocs<RelTy> relsA,
+ const InputSection *b, Relocs<RelTy> relsB);
bool equalsConstant(const InputSection *a, const InputSection *b);
bool equalsVariable(const InputSection *a, const InputSection *b);
@@ -235,8 +235,8 @@ void ICF<ELFT>::segregate(size_t begin, size_t end, uint32_t eqClassBase,
// Compare two lists of relocations.
template <class ELFT>
template <class RelTy>
-bool ICF<ELFT>::constantEq(const InputSection *secA, ArrayRef<RelTy> ra,
- const InputSection *secB, ArrayRef<RelTy> rb) {
+bool ICF<ELFT>::constantEq(const InputSection *secA, Relocs<RelTy> ra,
+ const InputSection *secB, Relocs<RelTy> rb) {
if (ra.size() != rb.size())
return false;
auto rai = ra.begin(), rae = ra.end(), rbi = rb.begin();
@@ -324,6 +324,8 @@ bool ICF<ELFT>::equalsConstant(const InputSection *a, const InputSection *b) {
const RelsOrRelas<ELFT> ra = a->template relsOrRelas<ELFT>();
const RelsOrRelas<ELFT> rb = b->template relsOrRelas<ELFT>();
+ if (ra.areRelocsCrel())
+ return constantEq(a, ra.crels, b, rb.crels);
return ra.areRelocsRel() || rb.areRelocsRel()
? constantEq(a, ra.rels, b, rb.rels)
: constantEq(a, ra.relas, b, rb.relas);
@@ -333,8 +335,8 @@ bool ICF<ELFT>::equalsConstant(const InputSection *a, const InputSection *b) {
// relocations point to the same section in terms of ICF.
template <class ELFT>
template <class RelTy>
-bool ICF<ELFT>::variableEq(const InputSection *secA, ArrayRef<RelTy> ra,
- const InputSection *secB, ArrayRef<RelTy> rb) {
+bool ICF<ELFT>::variableEq(const InputSection *secA, Relocs<RelTy> ra,
+ const InputSection *secB, Relocs<RelTy> rb) {
assert(ra.size() == rb.size());
auto rai = ra.begin(), rae = ra.end(), rbi = rb.begin();
@@ -374,6 +376,8 @@ template <class ELFT>
bool ICF<ELFT>::equalsVariable(const InputSection *a, const InputSection *b) {
const RelsOrRelas<ELFT> ra = a->template relsOrRelas<ELFT>();
const RelsOrRelas<ELFT> rb = b->template relsOrRelas<ELFT>();
+ if (ra.areRelocsCrel())
+ return variableEq(a, ra.crels, b, rb.crels);
return ra.areRelocsRel() || rb.areRelocsRel()
? variableEq(a, ra.rels, b, rb.rels)
: variableEq(a, ra.relas, b, rb.relas);
@@ -441,7 +445,7 @@ void ICF<ELFT>::forEachClass(llvm::function_ref<void(size_t, size_t)> fn) {
// hash.
template <class RelTy>
static void combineRelocHashes(unsigned cnt, InputSection *isec,
- ArrayRef<RelTy> rels) {
+ Relocs<RelTy> rels) {
uint32_t hash = isec->eqClass[cnt % 2];
for (RelTy rel : rels) {
Symbol &s = isec->file->getRelocTargetSym(rel);
@@ -505,7 +509,9 @@ template <class ELFT> void ICF<ELFT>::run() {
for (unsigned cnt = 0; cnt != 2; ++cnt) {
parallelForEach(sections, [&](InputSection *s) {
const RelsOrRelas<ELFT> rels = s->template relsOrRelas<ELFT>();
- if (rels.areRelocsRel())
+ if (rels.areRelocsCrel())
+ combineRelocHashes(cnt, s, rels.crels);
+ else if (rels.areRelocsRel())
combineRelocHashes(cnt, s, rels.rels);
else
combineRelocHashes(cnt, s, rels.relas);
diff --git a/lld/ELF/InputFiles.cpp b/lld/ELF/InputFiles.cpp
index 03ff4eadfe670..f1c0eb292361b 100644
--- a/lld/ELF/InputFiles.cpp
+++ b/lld/ELF/InputFiles.cpp
@@ -834,6 +834,7 @@ void ObjFile<ELFT>::initializeSections(bool ignoreComdats,
case SHT_STRTAB:
case SHT_REL:
case SHT_RELA:
+ case SHT_CREL:
case SHT_NULL:
break;
case SHT_PROGBITS:
diff --git a/lld/ELF/InputFiles.h b/lld/ELF/InputFiles.h
index 0617f41e1e13a..91d9273b48dfe 100644
--- a/lld/ELF/InputFiles.h
+++ b/lld/ELF/InputFiles.h
@@ -84,6 +84,7 @@ class InputFile {
assert(fileKind == ObjKind || fileKind == BinaryKind);
return sections;
}
+ void setSection(size_t i, InputSectionBase *s) { sections[i] = s; }
// Returns object file symbols. It is a runtime error to call this
// function on files of other types.
diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp
index 4420be77f6685..30816f13bab7c 100644
--- a/lld/ELF/InputSection.cpp
+++ b/lld/ELF/InputSection.cpp
@@ -133,21 +133,56 @@ void InputSectionBase::decompress() const {
compressed = false;
}
-template <class ELFT> RelsOrRelas<ELFT> InputSectionBase::relsOrRelas() const {
+template <class ELFT>
+RelsOrRelas<ELFT> InputSectionBase::relsOrRelas(bool supportsCrel) const {
if (relSecIdx == 0)
return {};
RelsOrRelas<ELFT> ret;
- typename ELFT::Shdr shdr =
- cast<ELFFileBase>(file)->getELFShdrs<ELFT>()[relSecIdx];
+ auto *f = cast<ObjFile<ELFT>>(file);
+ typename ELFT::Shdr shdr = f->template getELFShdrs<ELFT>()[relSecIdx];
+ if (shdr.sh_type == SHT_CREL) {
+ // Return an iterator if supported by caller.
+ if (supportsCrel) {
+ ret.crels = Relocs<typename ELFT::Crel>(
+ (const uint8_t *)f->mb.getBufferStart() + shdr.sh_offset);
+ return ret;
+ }
+ InputSectionBase *const &relSec = f->getSections()[relSecIdx];
+ // Otherwise, allocate a buffer to hold the decoded RELA relocations. When
+ // called for the first time, relSec is null (without --emit-relocs) or an
+ // InputSection with zero eqClass[0].
+ if (!relSec || !cast<InputSection>(relSec)->eqClass[0]) {
+ auto *sec = makeThreadLocal<InputSection>(*f, shdr, name);
+ f->setSection(relSecIdx, sec);
+ cast<InputSection>(sec)->eqClass[0] = SHT_RELA;
+
+ RelocsCrel<ELFT::Is64Bits> entries(sec->content_);
+ sec->size = entries.size();
+ auto *relas = makeThreadLocalN<typename ELFT::Rela>(entries.size());
+ sec->content_ = reinterpret_cast<uint8_t *>(relas);
+ size_t i = 0;
+ for (Elf_Crel_Impl<ELFT::Is64Bits> r : entries) {
+ relas[i].r_offset = r.r_offset;
+ relas[i].setSymbolAndType(r.r_symidx, r.r_type, false);
+ relas[i++].r_addend = r.r_addend;
+ }
+ }
+ ret.relas = {ArrayRef(
+ reinterpret_cast<const typename ELFT::Rela *>(relSec->content_),
+ relSec->size)};
+ return ret;
+ }
+
+ const void *content = f->mb.getBufferStart() + shdr.sh_offset;
+ size_t size = shdr.sh_size;
if (shdr.sh_type == SHT_REL) {
- ret.rels = ArrayRef(reinterpret_cast<const typename ELFT::Rel *>(
- file->mb.getBufferStart() + shdr.sh_offset),
- shdr.sh_size / sizeof(typename ELFT::Rel));
+ ret.rels = {ArrayRef(reinterpret_cast<const typename ELFT::Rel *>(content),
+ size / sizeof(typename ELFT::Rel))};
} else {
assert(shdr.sh_type == SHT_RELA);
- ret.relas = ArrayRef(reinterpret_cast<const typename ELFT::Rela *>(
- file->mb.getBufferStart() + shdr.sh_offset),
- shdr.sh_size / sizeof(typename ELFT::Rela));
+ ret.relas = {
+ ArrayRef(reinterpret_cast<const typename ELFT::Rela *>(content),
+ size / sizeof(typename ELFT::Rela))};
}
return ret;
}
@@ -906,7 +941,7 @@ uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type,
// So, we handle relocations for non-alloc sections directly in this
// function as a performance optimization.
template <class ELFT, class RelTy>
-void InputSection::relocateNonAlloc(uint8_t *buf, ArrayRef<RelTy> rels) {
+void InputSection::relocateNonAlloc(uint8_t *buf, Relocs<RelTy> rels) {
const unsigned bits = sizeof(typename ELFT::uint) * 8;
const TargetInfo &target = *elf::target;
const auto emachine = config->emachine;
@@ -1069,7 +1104,9 @@ void InputSectionBase::relocate(uint8_t *buf, uint8_t *bufEnd) {
// For a relocatable link, also call relocateNonAlloc() to rewrite applicable
// locations with tombstone values.
const RelsOrRelas<ELFT> rels = sec->template relsOrRelas<ELFT>();
- if (rels.areRelocsRel())
+ if (rels.areRelocsCrel())
+ sec->relocateNonAlloc<ELFT>(buf, rels.crels);
+ else if (rels.areRelocsRel())
sec->relocateNonAlloc<ELFT>(buf, rels.rels);
else
sec->relocateNonAlloc<ELFT>(buf, rels.relas);
@@ -1247,7 +1284,7 @@ SyntheticSection *EhInputSection::getParent() const {
// .eh_frame is a sequence of CIE or FDE records.
// This function splits an input section into records and returns them.
template <class ELFT> void EhInputSection::split() {
- const RelsOrRelas<ELFT> rels = relsOrRelas<ELFT>();
+ const RelsOrRelas<ELFT> rels = relsOrRelas<ELFT>(/*supportsCrel=*/false);
// getReloc expects the relocations to be sorted by r_offset. See the comment
// in scanRelocs.
if (rels.areRelocsRel()) {
@@ -1413,10 +1450,14 @@ template void InputSection::writeTo<ELF32BE>(uint8_t *);
template void InputSection::writeTo<ELF64LE>(uint8_t *);
template void InputSection::writeTo<ELF64BE>(uint8_t *);
-template RelsOrRelas<ELF32LE> InputSectionBase::relsOrRelas<ELF32LE>() const;
-template RelsOrRelas<ELF32BE> InputSectionBase::relsOrRelas<ELF32BE>() const;
-template RelsOrRelas<ELF64LE> InputSectionBase::relsOrRelas<ELF64LE>() const;
-template RelsOrRelas<ELF64BE> InputSectionBase::relsOrRelas<ELF64BE>() const;
+template RelsOrRelas<ELF32LE>
+InputSectionBase::relsOrRelas<ELF32LE>(bool) const;
+template RelsOrRelas<ELF32BE>
+InputSectionBase::relsOrRelas<ELF32BE>(bool) const;
+template RelsOrRelas<ELF64LE>
+InputSectionBase::relsOrRelas<ELF64LE>(bool) const;
+template RelsOrRelas<ELF64BE>
+InputSectionBase::relsOrRelas<ELF64BE>(bool) const;
template MergeInputSection::MergeInputSection(ObjFile<ELF32LE> &,
const ELF32LE::Shdr &, StringRef);
diff --git a/lld/ELF/InputSection.h b/lld/ELF/InputSection.h
index ec12235f842a9..ecfff284b1388 100644
--- a/lld/ELF/InputSection.h
+++ b/lld/ELF/InputSection.h
@@ -37,9 +37,11 @@ LLVM_LIBRARY_VISIBILITY extern std::vector<Partition> partitions;
// Returned by InputSectionBase::relsOrRelas. At least one member is empty.
template <class ELFT> struct RelsOrRelas {
- ArrayRef<typename ELFT::Rel> rels;
- ArrayRef<typename ELFT::Rela> relas;
+ Relocs<typename ELFT::Rel> rels;
+ Relocs<typename ELFT::Rela> relas;
+ Relocs<typename ELFT::Crel> crels;
bool areRelocsRel() const { return rels.size(); }
+ bool areRelocsCrel() const { return crels.size(); }
};
// This is the base class of all sections that lld handles. Some are sections in
@@ -200,7 +202,8 @@ class InputSectionBase : public SectionBase {
// used by --gc-sections.
InputSectionBase *nextInSectionGroup = nullptr;
- template <class ELFT> RelsOrRelas<ELFT> relsOrRelas() const;
+ template <class ELFT>
+ RelsOrRelas<ELFT> relsOrRelas(bool supportsCrel = true) const;
// InputSections that are dependent on us (reverse dependency for GC)
llvm::TinyPtrVector<InputSection *> dependentSections;
@@ -407,7 +410,7 @@ class InputSection : public InputSectionBase {
InputSectionBase *getRelocatedSection() const;
template <class ELFT, class RelTy>
- void relocateNonAlloc(uint8_t *buf, llvm::ArrayRef<RelTy> rels);
+ void relocateNonAlloc(uint8_t *buf, Relocs<RelTy> rels);
// Points to the canonical section. If ICF folds two sections, repl pointer of
// one section points to the other.
@@ -474,7 +477,8 @@ class SyntheticSection : public InputSection {
};
inline bool isStaticRelSecType(uint32_t type) {
- return type == llvm::ELF::SHT_RELA || type == llvm::ELF::SHT_REL;
+ return type == llvm::ELF::SHT_RELA || type == llvm::ELF::SHT_CREL ||
+ type == llvm::ELF::SHT_REL;
}
inline bool isDebugSection(const InputSectionBase &sec) {
diff --git a/lld/ELF/LinkerScript.cpp b/lld/ELF/LinkerScript.cpp
index e2208da18dce0..055fa21d44ca6 100644
--- a/lld/ELF/LinkerScript.cpp
+++ b/lld/ELF/LinkerScript.cpp
@@ -61,6 +61,8 @@ static StringRef getOutputSectionName(const InputSectionBase *s) {
assert(config->relocatable && (rel->flags & SHF_LINK_ORDER));
return s->name;
}
+ if (s->type == SHT_CREL)
+ return saver().save(".crel" + out->name);
if (s->type == SHT_RELA)
return saver().save(".rela" + out->name);
return saver().save(".rel" + out->name);
diff --git a/lld/ELF/MarkLive.cpp b/lld/ELF/MarkLive.cpp
index 45431e44a6c8c..e188b93e7e2b9 100644
--- a/lld/ELF/MarkLive.cpp
+++ b/lld/ELF/MarkLive.cpp
@@ -85,6 +85,12 @@ static uint64_t getAddend(InputSectionBase &sec,
return rel.r_addend;
}
+template <class ELFT>
+static uint64_t getAddend(InputSectionBase &sec,
+ const typename ELFT::Crel &rel) {
+ return rel.r_addend;
+}
+
template <class ELFT>
template <class RelTy>
void MarkLive<ELFT>::resolveReloc(InputSectionBase &sec, RelTy &rel,
@@ -239,7 +245,8 @@ template <class ELFT> void MarkLive<ELFT>::run() {
// all of them. We also want to preserve personality routines and LSDA
// referenced by .eh_frame sections, so we scan them for that here.
for (EhInputSection *eh : ctx.ehInputSections) {
- const RelsOrRelas<ELFT> rels = eh->template relsOrRelas<ELFT>();
+ const RelsOrRelas<ELFT> rels =
+ eh->template relsOrRelas<ELFT>(/*supportsCrel=*/false);
if (rels.areRelocsRel())
scanEhFrameSection(*eh, rels.rels);
else if (rels.relas.size())
@@ -310,6 +317,8 @@ template <class ELFT> void MarkLive<ELFT>::mark() {
resolveReloc(sec, rel, false);
for (const typename ELFT::Rela &rel : rels.relas)
resolveReloc(sec, rel, false);
+ for (const typename ELFT::Crel &rel : rels.crels)
+ resolveReloc(sec, rel, false);
for (InputSectionBase *isec : sec.dependentSections)
enqueue(isec, 0);
diff --git a/lld/ELF/OutputSections.cpp b/lld/ELF/OutputSections.cpp
index 60de10061c53d..709ede116c16f 100644
--- a/lld/ELF/OutputSections.cpp
+++ b/lld/ELF/OutputSections.cpp
@@ -18,6 +18,7 @@
#include "llvm/BinaryFormat/Dwarf.h"
#include "llvm/Config/llvm-config.h" // LLVM_ENABLE_ZLIB
#include "llvm/Support/Compression.h"
+#include "llvm/Support/LEB128.h"
#include "llvm/Support/Parallel.h"
#include "llvm/Support/Path.h"
#include "llvm/Support/TimeProfiler.h"
@@ -115,7 +116,19 @@ void OutputSection::recordSection(InputSectionBase *isec) {
// other InputSections.
void OutputSection::commitSection(InputSection *isec) {
if (LLVM_UNLIKELY(type != isec->type)) {
- if (hasInputSections || typeIsSet) {
+ if (!hasInputSections && !typeIsSet) {
+ type = isec->type;
+ } else if (isStaticRelSecType(type) && isStaticRelSecType(isec->type) &&
+ (type == SHT_CREL) != (isec->type == SHT_CREL)) {
+ // Combine mixed SHT_REL[A] and SHT_CREL to SHT_CREL.
+ type = SHT_CREL;
+ if (type == SHT_REL) {
+ if (name.consume_front(".rel"))
+ name = saver().save(".crel" + name);
+ } else if (name.consume_front(".rela")) {
+ name = saver().save(".crel" + name);
+ }
+ } else {
if (typeIsSet || !canMergeToProgbits(type) ||
!canMergeToProgbits(isec->type)) {
// The (NOLOAD) changes the section type to SHT_NOBITS, the intention is
@@ -133,8 +146,6 @@ void OutputSection::commitSection(InputSection *isec) {
}
if (!typeIsSet)
type = SHT_PROGBITS;
- } else {
- type = isec->type;
}
}
if (!hasInputSections) {
@@ -470,6 +481,11 @@ void OutputSection::writeTo(uint8_t *buf, parallel::TaskGroup &tg) {
llvm::TimeTraceScope timeScope("Write sections", name);
if (type == SHT_NOBITS)
return;
+ if (type == SHT_CREL && !(flags & SHF_ALLOC)) {
+ buf += encodeULEB128(crelHeader, buf);
+ memcpy(buf, crelBody.data(), crelBody.size());
+ return;
+ }
// If the section is compressed due to
// --compress-debug-section/--compress-sections, the content is already known.
@@ -592,6 +608,113 @@ static void finalizeShtGroup(OutputSection *os, InputSection *section) {
os->size = (1 + seen.size()) * sizeof(uint32_t);
}
+template <class uint>
+LLVM_ATTRIBUTE_ALWAYS_INLINE static void
+encodeOneCrel(raw_svector_ostream &os, uint &outOffset, uint32_t &outSymidx,
+ uint32_t &outType, uint &outAddend, uint offset,
+ const Symbol &sym, uint32_t type, uint addend) {
+ const auto deltaOffset = static_cast<uint64_t>(offset - outOffset);
+ outOffset = offset;
+ int64_t symidx = in.symTab->getSymbolIndex(sym);
+ if (sym.type == STT_SECTION) {
+ auto *d = dyn_cast<Defined>(&sym);
+ if (d) {
+ SectionBase *section = d->section;
+ assert(section->isLive());
+ addend = sym.getVA(addend) - section->getOutputSection()->addr;
+ } else {
+ // Encode R_*_NONE(symidx=0).
+ symidx = type = addend = 0;
+ }
+ }
+
+ // Similar to llvm::ELF::encodeCrel.
+ uint8_t b = deltaOffset * 8 + (outSymidx != symidx) +
+ (outType != type ? 2 : 0) + (outAddend != addend ? 4 : 0);
+ if (deltaOffset < 0x10) {
+ os << char(b);
+ } else {
+ os << char(b | 0x80);
+ encodeULEB128(deltaOffset >> 4, os);
+ }
+ if (b & 1) {
+ encodeSLEB128(static_cast<int32_t>(symidx - outSymidx), os);
+ outSymidx = symidx;
+ }
+ if (b & 2) {
+ encodeSLEB128(static_cast<int32_t>(type - outType), os);
+ outType = type;
+ }
+ if (b & 4) {
+ encodeSLEB128(std::make_signed_t<uint>(addend - outAddend), os);
+ outAddend = addend;
+ }
+}
+
+template <class ELFT>
+static size_t relToCrel(raw_svector_ostream &os, typename ELFT::uint &outOffset,
+ uint32_t &outSymidx, uint32_t &outType,
+ typename ELFT::uint &outAddend, InputSection *relSec,
+ InputSectionBase *sec) {
+ const auto &file = *cast<ELFFileBase>(relSec->file);
+ if (relSec->type == SHT_REL) {
+ errorOrWarn(toString(relSec) + ": REL cannot be converted to CREL");
+ return 0;
+ }
+ auto rels = relSec->getDataAs<typename ELFT::Rela>();
+ for (auto rel : rels) {
+ encodeOneCrel<typename ELFT::uint>(
+ os, outOffset, outSymidx, outType, outAddend, sec->getVA(rel.r_offset),
+ file.getRelocTargetSym(rel), rel.getType(config->isMips64EL),
+ getAddend<ELFT>(rel));
+ }
+ return rels.size();
+}
+
+// Compute the content of a non-alloc CREL section due to -r or --emit-relocs.
+// Input CREL sections are decoded while REL[A] need to be converted.
+template <bool is64> void OutputSection::finalizeNonAllocCrel() {
+ using uint = typename Elf_Crel_Impl<is64>::uint;
+ raw_svector_ostream os(crelBody);
+ uint64_t totalCount = 0;
+ uint outOffset = 0, outAddend = 0;
+ uint32_t outSymidx = 0, outType = 0;
+ assert(commands.size() == 1);
+ auto *isd = cast<InputSectionDescription>(commands[0]);
+ for (InputSection *relSec : isd->sections) {
+ const auto &file = *cast<ELFFileBase>(relSec->file);
+ InputSectionBase *sec = relSec->getRelocatedSection();
+ if (relSec->type == SHT_CREL) {
+ RelocsCrel<is64> entries(relSec->content_);
+ totalCount += entries.size();
+ for (Elf_Crel_Impl<is64> r : entries) {
+ encodeOneCrel<uint>(os, outOffset, outSymidx, outType, outAddend,
+ (uint)sec->getVA(r.r_offset),
+ file.getSymbol(r.r_symidx), r.r_type, r.r_addend);
+ }
+ continue;
+ }
+
+ // Convert REL[A] to CREL.
+ if constexpr (is64) {
+ totalCount += config->isLE
+ ? relToCrel<ELF64LE>(os, outOffset, outSymidx, outType,
+ outAddend, relSec, sec)
+ : relToCrel<ELF64BE>(os, outOffset, outSymidx, outType,
+ outAddend, relSec, sec);
+ } else {
+ totalCount += config->isLE
+ ? relToCrel<ELF32LE>(os, outOffset, outSymidx, outType,
+ outAddend, relSec, sec)
+ : relToCrel<ELF32BE>(os, outOffset, outSymidx, outType,
+ outAddend, relSec, sec);
+ }
+ }
+
+ crelHeader = totalCount * 8 + 4;
+ size = getULEB128Size(crelHeader) + crelBody.size();
+}
+
void OutputSection::finalize() {
InputSection *first = getFirstInputSection(this);
@@ -628,6 +751,13 @@ void OutputSection::finalize() {
InputSectionBase *s = first->getRelocatedSection();
info = s->getOutputSection()->sectionIndex;
flags |= SHF_INFO_LINK;
+ // Finalize the content of non-alloc CREL.
+ if (type == SHT_CREL) {
+ if (config->is64)
+ finalizeNonAllocCrel<true>();
+ else
+ finalizeNonAllocCrel<false>();
+ }
}
// Returns true if S is in one of the many forms the compiler driver may pass
diff --git a/lld/ELF/OutputSections.h b/lld/ELF/OutputSections.h
index 78fede48a23f2..8c0c52f34ac9f 100644
--- a/lld/ELF/OutputSections.h
+++ b/lld/ELF/OutputSections.h
@@ -84,6 +84,11 @@ class OutputSection final : public SectionBase {
Expr alignExpr;
Expr lmaExpr;
Expr subalignExpr;
+
+ // Used by non-alloc SHT_CREL to hold the header and content byte stream.
+ uint64_t crelHeader = 0;
+ SmallVector<char, 0> crelBody;
+
SmallVector<SectionCommand *, 0> commands;
SmallVector<StringRef, 0> phdrs;
std::optional<std::array<uint8_t, 4>> filler;
@@ -106,6 +111,7 @@ class OutputSection final : public SectionBase {
// DATA_RELRO_END.
bool relro = false;
+ template <bool is64> void finalizeNonAllocCrel();
void finalize();
template <class ELFT>
void writeTo(uint8_t *buf, llvm::parallel::TaskGroup &tg);
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index da4724d8f6536..a233e18c92bab 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -475,8 +475,9 @@ class RelocationScanner {
uint64_t relOff) const;
void processAux(RelExpr expr, RelType type, uint64_t offset, Symbol &sym,
int64_t addend) const;
- template <class ELFT, class RelTy> void scanOne(RelTy *&i);
- template <class ELFT, class RelTy> void scan(ArrayRef<RelTy> rels);
+ template <class ELFT, class RelTy>
+ void scanOne(typename Relocs<RelTy>::const_iterator &i);
+ template <class ELFT, class RelTy> void scan(Relocs<RelTy> rels);
};
} // namespace
@@ -1433,12 +1434,13 @@ static unsigned handleTlsRelocation(RelType type, Symbol &sym,
return 0;
}
-template <class ELFT, class RelTy> void RelocationScanner::scanOne(RelTy *&i) {
+template <class ELFT, class RelTy>
+void RelocationScanner::scanOne(typename Relocs<RelTy>::const_iterator &i) {
const RelTy &rel = *i;
uint32_t symIndex = rel.getSymbol(config->isMips64EL);
Symbol &sym = sec->getFile<ELFT>()->getSymbol(symIndex);
RelType type;
- if constexpr (ELFT::Is64Bits) {
+ if constexpr (ELFT::Is64Bits || RelTy::IsCrel) {
type = rel.getType(config->isMips64EL);
++i;
} else {
@@ -1474,37 +1476,39 @@ template <class ELFT, class RelTy> void RelocationScanner::scanOne(RelTy *&i) {
maybeReportUndefined(cast<Undefined>(sym), *sec, offset))
return;
- if (config->emachine == EM_PPC64) {
- // We can separate the small code model relocations into 2 categories:
- // 1) Those that access the compiler generated .toc sections.
- // 2) Those that access the linker allocated got entries.
- // lld allocates got entries to symbols on demand. Since we don't try to
- // sort the got entries in any way, we don't have to track which objects
- // have got-based small code model relocs. The .toc sections get placed
- // after the end of the linker allocated .got section and we do sort those
- // so sections addressed with small code model relocations come first.
- if (type == R_PPC64_TOC16 || type == R_PPC64_TOC16_DS)
- sec->file->ppc64SmallCodeModelTocRelocs = true;
-
- // Record the TOC entry (.toc + addend) as not relaxable. See the comment in
- // InputSectionBase::relocateAlloc().
- if (type == R_PPC64_TOC16_LO && sym.isSection() && isa<Defined>(sym) &&
- cast<Defined>(sym).section->name == ".toc")
- ppc64noTocRelax.insert({&sym, addend});
-
- if ((type == R_PPC64_TLSGD && expr == R_TLSDESC_CALL) ||
- (type == R_PPC64_TLSLD && expr == R_TLSLD_HINT)) {
- if (i == end) {
- errorOrWarn("R_PPC64_TLSGD/R_PPC64_TLSLD may not be the last "
- "relocation" +
- getLocation(*sec, sym, offset));
- return;
- }
+ if constexpr (!RelTy::IsCrel) {
+ if (config->emachine == EM_PPC64) {
+ // We can separate the small code model relocations into 2 categories:
+ // 1) Those that access the compiler generated .toc sections.
+ // 2) Those that access the linker allocated got entries.
+ // lld allocates got entries to symbols on demand. Since we don't try to
+ // sort the got entries in any way, we don't have to track which objects
+ // have got-based small code model relocs. The .toc sections get placed
+ // after the end of the linker allocated .got section and we do sort those
+ // so sections addressed with small code model relocations come first.
+ if (type == R_PPC64_TOC16 || type == R_PPC64_TOC16_DS)
+ sec->file->ppc64SmallCodeModelTocRelocs = true;
+
+ // Record the TOC entry (.toc + addend) as not relaxable. See the comment
+ // in InputSectionBase::relocateAlloc().
+ if (type == R_PPC64_TOC16_LO && sym.isSection() && isa<Defined>(sym) &&
+ cast<Defined>(sym).section->name == ".toc")
+ ppc64noTocRelax.insert({&sym, addend});
+
+ if ((type == R_PPC64_TLSGD && expr == R_TLSDESC_CALL) ||
+ (type == R_PPC64_TLSLD && expr == R_TLSLD_HINT)) {
+ if (i == end) {
+ errorOrWarn("R_PPC64_TLSGD/R_PPC64_TLSLD may not be the last "
+ "relocation" +
+ getLocation(*sec, sym, offset));
+ return;
+ }
- // Offset the 4-byte aligned R_PPC64_TLSGD by one byte in the NOTOC case,
- // so we can discern it later from the toc-case.
- if (i->getType(/*isMips64EL=*/false) == R_PPC64_REL24_NOTOC)
- ++offset;
+ // Offset the 4-byte aligned R_PPC64_TLSGD by one byte in the NOTOC
+ // case, so we can discern it later from the toc-case.
+ if (i->getType(/*isMips64EL=*/false) == R_PPC64_REL24_NOTOC)
+ ++offset;
+ }
}
}
@@ -1542,7 +1546,7 @@ template <class ELFT, class RelTy> void RelocationScanner::scanOne(RelTy *&i) {
// instructions are generated by very old IBM XL compilers. Work around the
// issue by disabling GD/LD to IE/LE relaxation.
template <class RelTy>
-static void checkPPC64TLSRelax(InputSectionBase &sec, ArrayRef<RelTy> rels) {
+static void checkPPC64TLSRelax(InputSectionBase &sec, Relocs<RelTy> rels) {
// Skip if sec is synthetic (sec.file is null) or if sec has been marked.
if (!sec.file || sec.file->ppc64DisableTLSRelax)
return;
@@ -1574,7 +1578,7 @@ static void checkPPC64TLSRelax(InputSectionBase &sec, ArrayRef<RelTy> rels) {
}
template <class ELFT, class RelTy>
-void RelocationScanner::scan(ArrayRef<RelTy> rels) {
+void RelocationScanner::scan(Relocs<RelTy> rels) {
// Not all relocations end up in Sec->Relocations, but a lot do.
sec->relocations.reserve(rels.size());
@@ -1592,7 +1596,7 @@ void RelocationScanner::scan(ArrayRef<RelTy> rels) {
end = static_cast<const void *>(rels.end());
for (auto i = rels.begin(); i != end;)
- scanOne<ELFT>(i);
+ scanOne<ELFT, RelTy>(i);
// Sort relocations by offset for more efficient searching for
// R_RISCV_PCREL_HI20 and R_PPC64_ADDR64.
@@ -1608,7 +1612,9 @@ template <class ELFT> void RelocationScanner::scanSection(InputSectionBase &s) {
sec = &s;
getter = OffsetGetter(s);
const RelsOrRelas<ELFT> rels = s.template relsOrRelas<ELFT>();
- if (rels.areRelocsRel())
+ if (rels.areRelocsCrel())
+ scan<ELFT>(rels.crels);
+ else if (rels.areRelocsRel())
scan<ELFT>(rels.rels);
else
scan<ELFT>(rels.relas);
diff --git a/lld/ELF/Relocations.h b/lld/ELF/Relocations.h
index e299d23dd7db3..24cb09827be5b 100644
--- a/lld/ELF/Relocations.h
+++ b/lld/ELF/Relocations.h
@@ -12,6 +12,7 @@
#include "lld/Common/LLVM.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/Object/ELFTypes.h"
#include <vector>
namespace lld::elf {
@@ -204,6 +205,88 @@ class ThunkCreator {
uint32_t pass = 0;
};
+// Decode LEB128 without error checking. Only used by performance critical code
+// like RelocsCrel.
+inline uint64_t readLEB128(const uint8_t *&p, uint64_t leb) {
+ uint64_t acc = 0, shift = 0, byte;
+ do {
+ byte = *p++;
+ acc |= (byte - 128 * (byte >= leb)) << shift;
+ shift += 7;
+ } while (byte >= 128);
+ return acc;
+}
+inline uint64_t readULEB128(const uint8_t *&p) { return readLEB128(p, 128); }
+inline int64_t readSLEB128(const uint8_t *&p) { return readLEB128(p, 64); }
+
+// This class implements a CREL iterator that does not allocate extra memory.
+template <bool is64> struct RelocsCrel {
+ using uint = std::conditional_t<is64, uint64_t, uint32_t>;
+ struct const_iterator {
+ uint32_t count;
+ uint8_t flagBits, shift;
+ const uint8_t *p;
+ llvm::object::Elf_Crel_Impl<is64> crel{};
+ const_iterator(size_t hdr, const uint8_t *p)
+ : count(hdr / 8), flagBits(hdr & 4 ? 3 : 2), shift(hdr % 4), p(p) {
+ if (count)
+ step();
+ }
+ void step() {
+ // See object::decodeCrel.
+ const uint8_t b = *p++;
+ crel.r_offset += b >> flagBits << shift;
+ if (b >= 0x80)
+ crel.r_offset +=
+ ((readULEB128(p) << (7 - flagBits)) - (0x80 >> flagBits)) << shift;
+ if (b & 1)
+ crel.r_symidx += readSLEB128(p);
+ if (b & 2)
+ crel.r_type += readSLEB128(p);
+ if (b & 4 && flagBits == 3)
+ crel.r_addend += static_cast<uint>(readSLEB128(p));
+ }
+ llvm::object::Elf_Crel_Impl<is64> operator*() const { return crel; };
+ const llvm::object::Elf_Crel_Impl<is64> *operator->() const {
+ return &crel;
+ }
+ bool operator!=(const const_iterator &r) const { return count != r.count; }
+ const_iterator &operator++() {
+ if (--count)
+ step();
+ return *this;
+ }
+ void operator+=(size_t n) {
+ for (; n; --n)
+ operator++();
+ }
+
+ // R_PPC64_REL24_NOTOC in Relocations.cpp
+ explicit operator const void *() const { return nullptr; }
+ bool operator==(const void *) const { return !count; }
+ bool operator!=(const void *) const { return count; }
+ };
+
+ size_t hdr = 0;
+ const uint8_t *p = nullptr;
+
+ constexpr RelocsCrel() = default;
+ RelocsCrel(const uint8_t *p) : hdr(readULEB128(p)) { this->p = p; }
+ size_t size() const { return hdr / 8; }
+ const_iterator begin() const { return {hdr, p}; }
+ const_iterator end() const { return {0, nullptr}; }
+};
+
+template <class RelTy> struct Relocs : ArrayRef<RelTy> {
+ Relocs() = default;
+ Relocs(ArrayRef<RelTy> a) : ArrayRef<RelTy>(a) {}
+};
+
+template <bool is64>
+struct Relocs<llvm::object::Elf_Crel_Impl<is64>> : RelocsCrel<is64> {
+ using RelocsCrel<is64>::RelocsCrel;
+};
+
// Return a int64_t to make sure we get the sign extension out of the way as
// early as possible.
template <class ELFT>
@@ -214,20 +297,32 @@ template <class ELFT>
static inline int64_t getAddend(const typename ELFT::Rela &rel) {
return rel.r_addend;
}
+template <class ELFT>
+static inline int64_t getAddend(const typename ELFT::Crel &rel) {
+ return rel.r_addend;
+}
template <typename RelTy>
-ArrayRef<RelTy> sortRels(ArrayRef<RelTy> rels, SmallVector<RelTy, 0> &storage) {
+inline Relocs<RelTy> sortRels(Relocs<RelTy> rels,
+ SmallVector<RelTy, 0> &storage) {
auto cmp = [](const RelTy &a, const RelTy &b) {
return a.r_offset < b.r_offset;
};
if (!llvm::is_sorted(rels, cmp)) {
storage.assign(rels.begin(), rels.end());
llvm::stable_sort(storage, cmp);
- rels = storage;
+ rels = Relocs<RelTy>(storage);
}
return rels;
}
+template <bool is64>
+inline Relocs<llvm::object::Elf_Crel_Impl<is64>>
+sortRels(Relocs<llvm::object::Elf_Crel_Impl<is64>> rels,
+ SmallVector<llvm::object::Elf_Crel_Impl<is64>, 0> &storage) {
+ return {};
+}
+
// Returns true if Expr refers a GOT entry. Note that this function returns
// false for TLS variables even though they need GOT, because TLS variables uses
// GOT differently than the regular variables.
diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp
index 5d3f3df216b85..d64ae436152fe 100644
--- a/lld/ELF/SyntheticSections.cpp
+++ b/lld/ELF/SyntheticSections.cpp
@@ -455,7 +455,8 @@ template <class ELFT>
void EhFrameSection::addSectionAux(EhInputSection *sec) {
if (!sec->isLive())
return;
- const RelsOrRelas<ELFT> rels = sec->template relsOrRelas<ELFT>();
+ const RelsOrRelas<ELFT> rels =
+ sec->template relsOrRelas<ELFT>(/*supportsCrel=*/false);
if (rels.areRelocsRel())
addRecords<ELFT>(sec, rels.rels);
else
@@ -489,7 +490,8 @@ void EhFrameSection::iterateFDEWithLSDA(
DenseSet<size_t> ciesWithLSDA;
for (EhInputSection *sec : sections) {
ciesWithLSDA.clear();
- const RelsOrRelas<ELFT> rels = sec->template relsOrRelas<ELFT>();
+ const RelsOrRelas<ELFT> rels =
+ sec->template relsOrRelas<ELFT>(/*supportsCrel=*/false);
if (rels.areRelocsRel())
iterateFDEWithLSDAAux<ELFT>(*sec, rels.rels, ciesWithLSDA, fn);
else
@@ -3203,7 +3205,7 @@ template <class ELFT> DebugNamesSection<ELFT>::DebugNamesSection() {
template <class ELFT>
template <class RelTy>
void DebugNamesSection<ELFT>::getNameRelocs(
- InputSection *sec, ArrayRef<RelTy> rels,
+ InputSection *sec, Relocs<RelTy> rels,
DenseMap<uint32_t, uint32_t> &relocs) {
for (const RelTy &rel : rels) {
Symbol &sym = sec->file->getRelocTargetSym(rel);
@@ -3217,7 +3219,9 @@ template <class ELFT> void DebugNamesSection<ELFT>::finalizeContents() {
parallelFor(0, numChunks, [&](size_t i) {
InputSection *sec = inputSections[i];
auto rels = sec->template relsOrRelas<ELFT>();
- if (rels.areRelocsRel())
+ if (rels.areRelocsCrel())
+ getNameRelocs(sec, rels.crels, relocs.get()[i]);
+ else if (rels.areRelocsRel())
getNameRelocs(sec, rels.rels, relocs.get()[i]);
else
getNameRelocs(sec, rels.relas, relocs.get()[i]);
diff --git a/lld/ELF/SyntheticSections.h b/lld/ELF/SyntheticSections.h
index eaa09ea7194fb..f05e2ae95c5b4 100644
--- a/lld/ELF/SyntheticSections.h
+++ b/lld/ELF/SyntheticSections.h
@@ -916,7 +916,7 @@ class DebugNamesSection final : public DebugNamesBaseSection {
void writeTo(uint8_t *buf) override;
template <class RelTy>
- void getNameRelocs(InputSection *sec, ArrayRef<RelTy> rels,
+ void getNameRelocs(InputSection *sec, Relocs<RelTy> rels,
llvm::DenseMap<uint32_t, uint32_t> &relocs);
private:
diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp
index bce3cd2de7ed2..f83397cc28a2d 100644
--- a/lld/ELF/Writer.cpp
+++ b/lld/ELF/Writer.cpp
@@ -401,10 +401,19 @@ template <class ELFT> static void markUsedLocalSymbols() {
InputSection *isec = dyn_cast_or_null<InputSection>(s);
if (!isec)
continue;
- if (isec->type == SHT_REL)
+ if (isec->type == SHT_REL) {
markUsedLocalSymbolsImpl(f, isec->getDataAs<typename ELFT::Rel>());
- else if (isec->type == SHT_RELA)
+ } else if (isec->type == SHT_RELA) {
markUsedLocalSymbolsImpl(f, isec->getDataAs<typename ELFT::Rela>());
+ } else if (isec->type == SHT_CREL) {
+ // The is64=true variant also works with ELF32 since only the r_symidx
+ // member is used.
+ for (Elf_Crel_Impl<true> r : RelocsCrel<true>(isec->content_)) {
+ Symbol &sym = file->getSymbol(r.r_symidx);
+ if (sym.isLocal())
+ sym.used = true;
+ }
+ }
}
}
}
diff --git a/lld/test/ELF/crel-rel-mixed.s b/lld/test/ELF/crel-rel-mixed.s
new file mode 100644
index 0000000000000..a69fa1c09b436
--- /dev/null
+++ b/lld/test/ELF/crel-rel-mixed.s
@@ -0,0 +1,22 @@
+# REQUIRES: arm
+# RUN: rm -rf %t && split-file %s %t && cd %t
+# RUN: llvm-mc -filetype=obj -triple=armv7a -crel a.s -o a.o
+# RUN: llvm-mc -filetype=obj -triple=armv7a b.s -o b.o
+# RUN: not ld.lld -r a.o b.o 2>&1 | FileCheck %s --check-prefix=ERR
+
+# ERR: error: b.o:(.rel.text): REL cannot be converted to CREL
+
+#--- a.s
+.global _start, foo
+_start:
+ bl foo
+ bl .text.foo
+
+.section .text.foo,"ax"
+foo:
+ nop
+
+#--- b.s
+.globl fb
+fb:
+ bl fb
diff --git a/lld/test/ELF/crel.s b/lld/test/ELF/crel.s
new file mode 100644
index 0000000000000..ac09e94e223da
--- /dev/null
+++ b/lld/test/ELF/crel.s
@@ -0,0 +1,81 @@
+# REQUIRES: x86
+# RUN: rm -rf %t && split-file %s %t && cd %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64 -crel a.s -o a.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64 -crel b.s -o b.o
+# RUN: ld.lld -pie a.o b.o -o out
+# RUN: llvm-objdump -d out | FileCheck %s
+# RUN: llvm-readelf -Srs out | FileCheck %s --check-prefix=RELOC
+
+# CHECK: <_start>:
+# CHECK-NEXT: callq {{.*}} <foo>
+# CHECK-NEXT: callq {{.*}} <foo>
+# CHECK-EMPTY:
+# CHECK-NEXT: <foo>:
+# CHECK-NEXT: leaq {{.*}} # 0x27c
+# CHECK-NEXT: leaq {{.*}} # 0x278
+
+# RELOC: .data PROGBITS {{0*}}[[#%x,DATA:]]
+
+# RELOC: {{0*}}[[#DATA+8]] 0000000000000008 R_X86_64_RELATIVE [[#%x,DATA+0x8000000000000000]]
+
+# RUN: ld.lld -pie --emit-relocs a.o b.o -o out1
+# RUN: llvm-objdump -dr out1 | FileCheck %s --check-prefix=CHECKE
+# RUN: llvm-readelf -Sr out1 | FileCheck %s --check-prefix=RELOCE
+
+# CHECKE: <_start>:
+# CHECKE-NEXT: callq {{.*}} <foo>
+# CHECKE-NEXT: R_X86_64_PLT32 foo-0x4
+# CHECKE-NEXT: callq {{.*}} <foo>
+# CHECKE-NEXT: R_X86_64_PLT32 .text+0x6
+# CHECKE-EMPTY:
+# CHECKE-NEXT: <foo>:
+# CHECKE-NEXT: leaq {{.*}}
+# CHECKE-NEXT: R_X86_64_PC32 .L.str-0x4
+# CHECKE-NEXT: leaq {{.*}}
+# CHECKE-NEXT: R_X86_64_PC32 .L.str1-0x4
+
+# RELOCE: .rodata PROGBITS {{0*}}[[#%x,RO:]]
+# RELOCE: .data PROGBITS {{0*}}[[#%x,DATA:]]
+
+# RELOCE: Relocation section '.crel.data' at offset 0x3c8 contains 2 entries:
+# RELOCE-NEXT: Offset Info Type Symbol's Value Symbol's Name + Addend
+# RELOCE-NEXT: {{0*}}[[#DATA+8]] {{.*}} R_X86_64_64 {{.*}} .data - 8000000000000000
+# RELOCE-NEXT: {{0*}}[[#DATA+24]]{{.*}} R_X86_64_64 {{.*}} .data - 1
+# RELOCE: Relocation section '.crel.rodata' at offset {{.*}} contains 4 entries:
+# RELOCE-NEXT: Offset Info Type Symbol's Value Symbol's Name + Addend
+# RELOCE-NEXT: {{0*}}[[#RO+8]] {{.*}} R_X86_64_PC32 {{.*}} foo + 0
+# RELOCE-NEXT: {{0*}}[[#RO+23]] {{.*}} R_X86_64_PC32 {{.*}} foo + 3f
+# RELOCE-NEXT: {{0*}}[[#RO+39]] {{.*}} R_X86_64_PC64 {{.*}} foo + 7f
+# RELOCE-NEXT: {{0*}}[[#RO+47]] {{.*}} R_X86_64_PC32 {{.*}} _start - 1f81
+
+#--- a.s
+.global _start, foo
+_start:
+ call foo
+ call .text.foo
+
+.section .text.foo,"ax"
+foo:
+ leaq .L.str(%rip), %rsi
+ leaq .L.str1(%rip), %rsi
+
+.section .rodata.str1.1,"aMS", at progbits,1
+.L.str:
+ .asciz "abc"
+.L.str1:
+ .asciz "def"
+
+.data
+.quad 0
+.quad .data - 0x8000000000000000
+.quad 0
+.quad .data - 1
+
+#--- b.s
+.section .rodata,"a"
+.long foo - .
+.space 15-4
+.long foo - . + 63 # offset+=15
+.space 16-4
+.quad foo - . + 127 # offset+=16
+.long _start - . - 8065
diff --git a/lld/test/ELF/debug-names.s b/lld/test/ELF/debug-names.s
index 888dd9007ed12..1bbb07b065e33 100644
--- a/lld/test/ELF/debug-names.s
+++ b/lld/test/ELF/debug-names.s
@@ -10,7 +10,7 @@
# REQUIRES: x86
# RUN: rm -rf %t && split-file %s %t && cd %t
-# RUN: llvm-mc -filetype=obj -triple=x86_64 a.s -o a.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64 --crel a.s -o a.o
# RUN: llvm-mc -filetype=obj -triple=x86_64 b.s -o b.o
# RUN: ld.lld --debug-names --no-debug-names a.o b.o -o out0
diff --git a/lld/test/ELF/gc-sections.s b/lld/test/ELF/gc-sections.s
index 94adc8210b4bc..31e00d495146a 100644
--- a/lld/test/ELF/gc-sections.s
+++ b/lld/test/ELF/gc-sections.s
@@ -8,6 +8,10 @@
# RUN: ld.lld --export-dynamic --gc-sections %t -o %t2
# RUN: llvm-readobj --sections --symbols %t2 | FileCheck -check-prefix=GC2 %s
+# RUN: llvm-mc -filetype=obj -triple=x86_64 --crel %s -o %t.o
+# RUN: ld.lld --gc-sections --print-gc-sections %t.o -o %t2 | FileCheck --check-prefix=GC1-DISCARD %s
+# RUN: llvm-readobj --sections --symbols %t2 | FileCheck -check-prefix=GC1 %s
+
# NOGC: Name: .eh_frame
# NOGC: Name: .text
# NOGC: Name: .init
diff --git a/lld/test/ELF/icf1.s b/lld/test/ELF/icf1.s
index 5c6e667d53c78..9682b06f4606f 100644
--- a/lld/test/ELF/icf1.s
+++ b/lld/test/ELF/icf1.s
@@ -3,6 +3,9 @@
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
# RUN: ld.lld %t -o /dev/null --icf=all --print-icf-sections | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=x86_64 --crel %s -o %t
+# RUN: ld.lld %t -o /dev/null --icf=all --print-icf-sections | FileCheck %s
+
# CHECK: selected section {{.*}}:(.text.f1)
# CHECK: removing identical section {{.*}}:(.text.f2)
diff --git a/lld/test/ELF/icf4.s b/lld/test/ELF/icf4.s
index ff13a7ebff3da..310577a55c0d8 100644
--- a/lld/test/ELF/icf4.s
+++ b/lld/test/ELF/icf4.s
@@ -1,6 +1,6 @@
# REQUIRES: x86
-# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t
+# RUN: llvm-mc --crel -filetype=obj -triple=x86_64-unknown-linux %s -o %t
# RUN: ld.lld %t -o /dev/null --icf=all --print-icf-sections | count 0
.globl _start, f1, f2
diff --git a/lld/test/ELF/relocatable-crel-32.s b/lld/test/ELF/relocatable-crel-32.s
new file mode 100644
index 0000000000000..8fbf236d77452
--- /dev/null
+++ b/lld/test/ELF/relocatable-crel-32.s
@@ -0,0 +1,71 @@
+# REQUIRES: ppc
+# RUN: rm -rf %t && split-file %s %t && cd %t
+# RUN: llvm-mc -filetype=obj -triple=powerpc -crel a.s -o a.o
+# RUN: llvm-mc -filetype=obj -triple=powerpc -crel b.s -o b.o
+# RUN: ld.lld -r b.o a.o -o out
+# RUN: llvm-readobj -r out | FileCheck %s --check-prefixes=CHECK,CRELFOO
+
+# RUN: llvm-mc -filetype=obj -triple=powerpc a.s -o a1.o
+# RUN: ld.lld -r b.o a1.o -o out1
+# RUN: llvm-readobj -r out1 | FileCheck %s --check-prefixes=CHECK,RELAFOO
+# RUN: ld.lld -r a1.o b.o -o out2
+# RUN: llvm-readobj -r out2 | FileCheck %s --check-prefixes=CHECK2
+
+# CHECK: Relocations [
+# CHECK-NEXT: Section (2) .crel.text {
+# CHECK-NEXT: 0x0 R_PPC_REL24 fb 0x0
+# CHECK-NEXT: 0x4 R_PPC_REL24 foo 0x0
+# CHECK-NEXT: 0x8 R_PPC_REL24 .text.foo 0x0
+# CHECK-NEXT: 0xE R_PPC_ADDR16_HA .rodata.str1.1 0x4
+# CHECK-NEXT: 0x12 R_PPC_ADDR16_LO .rodata.str1.1 0x4
+# CHECK-NEXT: 0x16 R_PPC_ADDR16_HA .rodata.str1.1 0x0
+# CHECK-NEXT: 0x1A R_PPC_ADDR16_LO .rodata.str1.1 0x0
+# CHECK-NEXT: }
+# CRELFOO-NEXT: Section (4) .crel.text.foo {
+# RELAFOO-NEXT: Section (4) .rela.text.foo {
+# CHECK-NEXT: 0x0 R_PPC_REL24 g 0x0
+# CHECK-NEXT: 0x4 R_PPC_REL24 g 0x0
+# CHECK-NEXT: }
+# CHECK-NEXT: ]
+
+# CHECK2: Relocations [
+# CHECK2-NEXT: Section (2) .crel.text {
+# CHECK2-NEXT: 0x0 R_PPC_REL24 foo 0x0
+# CHECK2-NEXT: 0x4 R_PPC_REL24 .text.foo 0x0
+# CHECK2-NEXT: 0xA R_PPC_ADDR16_HA .rodata.str1.1 0x4
+# CHECK2-NEXT: 0xE R_PPC_ADDR16_LO .rodata.str1.1 0x4
+# CHECK2-NEXT: 0x12 R_PPC_ADDR16_HA .rodata.str1.1 0x0
+# CHECK2-NEXT: 0x16 R_PPC_ADDR16_LO .rodata.str1.1 0x0
+# CHECK2-NEXT: 0x18 R_PPC_REL24 fb 0x0
+# CHECK2-NEXT: }
+# CHECK2-NEXT: Section (4) .rela.text.foo {
+# CHECK2-NEXT: 0x0 R_PPC_REL24 g 0x0
+# CHECK2-NEXT: 0x4 R_PPC_REL24 g 0x0
+# CHECK2-NEXT: }
+# CHECK2-NEXT: ]
+
+#--- a.s
+.global _start, foo
+_start:
+ bl foo
+ bl .text.foo
+ lis 3, .L.str at ha
+ la 3, .L.str at l(3)
+ lis 3, .L.str1 at ha
+ la 3, .L.str1 at l(3)
+
+.section .text.foo,"ax"
+foo:
+ bl g
+ bl g
+
+.section .rodata.str1.1,"aMS", at progbits,1
+.L.str:
+ .asciz "abc"
+.L.str1:
+ .asciz "def"
+
+#--- b.s
+.globl fb
+fb:
+ bl fb
diff --git a/lld/test/ELF/relocatable-crel.s b/lld/test/ELF/relocatable-crel.s
new file mode 100644
index 0000000000000..6e97c3e24d66c
--- /dev/null
+++ b/lld/test/ELF/relocatable-crel.s
@@ -0,0 +1,107 @@
+# REQUIRES: x86
+# RUN: rm -rf %t && split-file %s %t && cd %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64 -crel a.s -o a.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64 -crel b.s -o b.o
+# RUN: ld.lld -r b.o a.o -o out
+# RUN: llvm-readobj -r out | FileCheck %s --check-prefixes=CHECK,CRELFOO
+
+# RUN: llvm-mc -filetype=obj -triple=x86_64 a.s -o a1.o
+# RUN: ld.lld -r b.o a1.o -o out1
+# RUN: llvm-readobj -r out1 | FileCheck %s --check-prefixes=CHECK,RELAFOO
+# RUN: ld.lld -r a1.o b.o -o out2
+# RUN: llvm-readobj -r out2 | FileCheck %s --check-prefixes=CHECK2
+
+# CHECK: Relocations [
+# CHECK-NEXT: .crel.text {
+# CHECK-NEXT: 0x1 R_X86_64_PLT32 fb 0xFFFFFFFFFFFFFFFC
+# CHECK-NEXT: 0x9 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+# CHECK-NEXT: 0xE R_X86_64_PLT32 .text.foo 0xFFFFFFFFFFFFFFFC
+# CHECK-NEXT: }
+# CHECK-NEXT: .crel.rodata {
+# CHECK-NEXT: 0x0 R_X86_64_PC32 foo 0x0
+# CHECK-NEXT: 0xF R_X86_64_PC32 foo 0x3F
+# CHECK-NEXT: 0x1F R_X86_64_PC64 foo 0x7F
+# CHECK-NEXT: 0x27 R_X86_64_PC32 _start 0xFFFFFFFFFFFFE07F
+# CHECK-COUNT-12: R_X86_64_32 _start 0x0
+# CHECK-NEXT: }
+# CRELFOO-NEXT: .crel.text.foo {
+# RELAFOO-NEXT: .rela.text.foo {
+# CHECK-NEXT: 0x3 R_X86_64_PC32 .L.str 0xFFFFFFFFFFFFFFFC
+# CHECK-NEXT: 0xA R_X86_64_PC32 .L.str1 0xFFFFFFFFFFFFFFFC
+# CHECK-NEXT: 0xF R_X86_64_PLT32 g 0xFFFFFFFFFFFFFFFC
+# CHECK-NEXT: 0x14 R_X86_64_PLT32 g 0xFFFFFFFFFFFFFFFC
+# CHECK-NEXT: }
+# CRELFOO-NEXT: .crel.data {
+# RELAFOO-NEXT: .rela.data {
+# CHECK-NEXT: 0x8 R_X86_64_64 _start 0x8000000000000000
+# CHECK-NEXT: 0x18 R_X86_64_64 _start 0xFFFFFFFFFFFFFFFF
+# CHECK-NEXT: }
+# CHECK-NEXT: ]
+
+# CHECK2: Relocations [
+# CHECK2-NEXT: .crel.text {
+# CHECK2-NEXT: 0x1 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFC
+# CHECK2-NEXT: 0x6 R_X86_64_PLT32 .text.foo 0xFFFFFFFFFFFFFFFC
+# CHECK2-NEXT: 0xD R_X86_64_PLT32 fb 0xFFFFFFFFFFFFFFFC
+# CHECK2-NEXT: }
+# CHECK2-NEXT: .rela.text.foo {
+# CHECK2-NEXT: 0x3 R_X86_64_PC32 .L.str 0xFFFFFFFFFFFFFFFC
+# CHECK2-NEXT: 0xA R_X86_64_PC32 .L.str1 0xFFFFFFFFFFFFFFFC
+# CHECK2-NEXT: 0xF R_X86_64_PLT32 g 0xFFFFFFFFFFFFFFFC
+# CHECK2-NEXT: 0x14 R_X86_64_PLT32 g 0xFFFFFFFFFFFFFFFC
+# CHECK2-NEXT: }
+# CHECK2-NEXT: .rela.data {
+# CHECK2-NEXT: 0x8 R_X86_64_64 _start 0x8000000000000000
+# CHECK2-NEXT: 0x18 R_X86_64_64 _start 0xFFFFFFFFFFFFFFFF
+# CHECK2-NEXT: }
+# CHECK2-NEXT: .crel.rodata {
+# CHECK2-NEXT: 0x0 R_X86_64_PC32 foo 0x0
+# CHECK2-NEXT: 0xF R_X86_64_PC32 foo 0x3F
+# CHECK2-NEXT: 0x1F R_X86_64_PC64 foo 0x7F
+# CHECK2-NEXT: 0x27 R_X86_64_PC32 _start 0xFFFFFFFFFFFFE07F
+# CHECK2-COUNT-12: R_X86_64_32 _start 0x0
+# CHECK2-NEXT: }
+# CHECK2-NEXT: ]
+
+#--- a.s
+.global _start, foo
+_start:
+ call foo
+ call .text.foo
+
+.section .text.foo,"ax"
+foo:
+ leaq .L.str(%rip), %rsi
+ leaq .L.str1(%rip), %rsi
+ call g
+ call g
+
+.section .rodata.str1.1,"aMS", at progbits,1
+.L.str:
+ .asciz "abc"
+.L.str1:
+ .asciz "def"
+
+.data
+.quad 0
+.quad _start - 0x8000000000000000
+.quad 0
+.quad _start - 1
+
+#--- b.s
+.globl fb
+fb:
+ call fb
+
+.section .rodata,"a"
+.long foo - .
+.space 15-4
+.long foo - . + 63 # offset+=15
+.space 16-4
+.quad foo - . + 127 # offset+=16
+.long _start - . - 8065
+
+## Ensure .crel.rodata contains 16 relocations so that getULEB128Size(crelHeader) > 1.
+.rept 12
+.long _start
+.endr
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