[llvm] [RISCV] Move exact VLEN VLMAX transform to RISCVVectorPeephole (PR #100551)

Pengcheng Wang via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 25 05:52:40 PDT 2024


================
@@ -76,13 +78,44 @@ char RISCVVectorPeephole::ID = 0;
 INITIALIZE_PASS(RISCVVectorPeephole, DEBUG_TYPE, "RISC-V Fold Masks", false,
                 false)
 
-// If an AVL is a VLENB that's possibly scaled to be equal to VLMAX, convert it
-// to the VLMAX sentinel value.
+/// Check if an operand is an immediate or a materialized ADDI $x0, imm.
+std::optional<unsigned>
+RISCVVectorPeephole::getConstant(const MachineOperand &VL) const {
+  if (VL.isImm())
+    return VL.getImm();
+
+  MachineInstr *Def = MRI->getVRegDef(VL.getReg());
----------------
wangpc-pp wrote:

Is it possible that VL is not a register operand?

https://github.com/llvm/llvm-project/pull/100551


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