[llvm] [LV] Support binary and unary operations with EVL-vectorization (PR #93854)

[via llvm-commits]

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@@ -1140,6 +1144,53 @@ void VPWidenRecipe::execute(VPTransformState &State) {
 #endif
 }
 
+void VPWidenEVLRecipe::execute(VPTransformState &State) {
+  assert(State.UF == 1 && "Expected only UF == 1 when vectorizing with "
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LiqinWeng wrote:

Sorry, I don't know much about vectorized design. I would like to know why UF is forced to be set to 1?

https://github.com/llvm/llvm-project/pull/93854