[llvm] [AMDGPU] Inplace FI elimination during PEI for scalar copy instruction (PR #99556)

[Pankaj Dwivedi via llvm-commits]

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@@ -2555,12 +2555,33 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
                       TmpResultReg)
                   .addImm(ST.getWavefrontSizeLog2())
                   .addReg(FrameReg);
-              auto Add = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ADD_U32_e32),
-                                 TmpResultReg);
-              Add.addImm(Offset).addReg(TmpResultReg, RegState::Kill);
+
+              MachineInstrBuilder Add;
+              if ((Add = TII->getAddNoCarry(*MBB, MI, DL, TmpResultReg, *RS)) ==
+                  nullptr) {
+                // VCC is live and no SGPR is free.
+                // since emergency stack slot is already used for spilling VGPR
+                // scavenged? This a way around to avoid carry, need follow-up.
+                BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), ResultReg)
+                    .addImm(Offset);
+                Add = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MAD_I32_I24_e64),
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PankajDwivedi-25 wrote:

There are more cases need to be handled if i move handling inside, getAddNoCarry.
It hits assert(MIB->getOpcode() == AMDGPU::V_ADD_CO_U32_e64 && "Need to reuse carry out register");
where we are trying to handle !SALU cases.

for now I have left it custom handled.

https://github.com/llvm/llvm-project/pull/99556