[llvm] [Hexagon] Fix concat lowering for HVX for 64B vector length (PR #98318)

[Santanu Das via llvm-commits]

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@@ -1748,7 +1748,7 @@ HexagonTargetLowering::LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG)
 
   unsigned InpLen = ty(Op.getOperand(0)).getVectorNumElements();
   MVT ByteTy = MVT::getVectorVT(MVT::i8, HwLen);
-  SDValue S = DAG.getConstant(InpLen*BitBytes, dl, MVT::i32);
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quic-santdas wrote:

Thanks for your comment! Yes, it does in the testcase. The shufflevectors are lowered to vror instructions for rotation [v0 = vror(v1,r1)]. The rotation is calculated correctly now (r1 in this case). We can see the difference in generated assembly after this fix. 

https://github.com/llvm/llvm-project/pull/98318