[llvm] [RISCV][TTI] Properly model odd vector sized LD/ST operations (PR #100436)

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``````````bash
git-clang-format --diff 8fd9624cf729dd722a170a9dfd8f725966515231 95145f528c88a461d169412ef94cb84cae8dce7b --extensions cpp -- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index c110a398bd..251a335c93 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -1412,7 +1412,6 @@ InstructionCost RISCVTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
     }
     return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
                                   CostKind, OpInfo, I);
-
   }();
 
   // Assume memory ops cost scale with the number of vector registers

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https://github.com/llvm/llvm-project/pull/100436