[llvm] [GlobalIsel] Modernize truncate of ext. (PR #100338)
Thorsten Schütt via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 24 06:51:35 PDT 2024
https://github.com/tschuett updated https://github.com/llvm/llvm-project/pull/100338
>From 41b6026a1ab1e00d3ad337c2080e4d51f2c0114d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Wed, 24 Jul 2024 07:23:08 +0200
Subject: [PATCH 1/3] [GlobalIsel] Modernize truncate of ext.
Credits:
https://github.com/llvm/llvm-project/pull/90964
https://reviews.llvm.org/D87050
combine-trunc.mir
Functional changes intended.
---
.../llvm/CodeGen/GlobalISel/CombinerHelper.h | 10 +-
.../CodeGen/GlobalISel/GenericMachineInstrs.h | 15 ++
.../include/llvm/Target/GlobalISel/Combine.td | 32 ++--
.../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 34 ----
.../GlobalISel/CombinerHelperCasts.cpp | 42 ++++
.../AArch64/GlobalISel/arm64-atomic.ll | 48 ++---
.../AArch64/GlobalISel/arm64-pcsections.ll | 40 ++--
.../AArch64/GlobalISel/combine-trunc.mir | 179 ++++++++++++++----
8 files changed, 268 insertions(+), 132 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 37a56e12efcc3..47365c3be3b93 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -390,12 +390,6 @@ class CombinerHelper {
void applyCombineExtOfExt(MachineInstr &MI,
std::tuple<Register, unsigned> &MatchInfo);
- /// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
- bool matchCombineTruncOfExt(MachineInstr &MI,
- std::pair<Register, unsigned> &MatchInfo);
- void applyCombineTruncOfExt(MachineInstr &MI,
- std::pair<Register, unsigned> &MatchInfo);
-
/// Transform trunc (shl x, K) to shl (trunc x), K
/// if K < VT.getScalarSizeInBits().
///
@@ -886,6 +880,10 @@ class CombinerHelper {
bool matchShlOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo);
+ /// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
+ bool matchTruncateOfExt(const MachineInstr &Root, const MachineInstr &ExtMI,
+ BuildFnTy &MatchInfo);
+
private:
/// Checks for legality of an indexed variant of \p LdSt.
bool isIndexedLoadStoreLegal(GLoadStore &LdSt) const;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
index 80897953156a0..8b7e8c0fbf1f5 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -919,6 +919,21 @@ class GSUCmp : public GenericMachineInstr {
};
};
+/// Represents an integer-like extending operation.
+class GExtOp : public GCastOp {
+public:
+ static bool classof(const MachineInstr *MI) {
+ switch (MI->getOpcode()) {
+ case TargetOpcode::G_SEXT:
+ case TargetOpcode::G_ZEXT:
+ case TargetOpcode::G_ANYEXT:
+ return true;
+ default:
+ return false;
+ }
+ };
+};
+
} // namespace llvm
#endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 3ef0636ebf1c7..2362e77b54be2 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -839,15 +839,6 @@ def unmerge_zext_to_zext : GICombineRule<
(apply [{ Helper.applyCombineUnmergeZExtToZExt(*${d}); }])
>;
-// Fold trunc ([asz]ext x) -> x or ([asz]ext x) or (trunc x).
-def trunc_ext_fold_matchinfo : GIDefMatchData<"std::pair<Register, unsigned>">;
-def trunc_ext_fold: GICombineRule <
- (defs root:$root, trunc_ext_fold_matchinfo:$matchinfo),
- (match (wip_match_opcode G_TRUNC):$root,
- [{ return Helper.matchCombineTruncOfExt(*${root}, ${matchinfo}); }]),
- (apply [{ Helper.applyCombineTruncOfExt(*${root}, ${matchinfo}); }])
->;
-
// Under certain conditions, transform:
// trunc (shl x, K) -> shl (trunc x), K//
// trunc ([al]shr x, K) -> (trunc ([al]shr (trunc x), K))
@@ -1768,6 +1759,25 @@ def freeze_combines: GICombineGroup<[
push_freeze_to_prevent_poison_from_propagating
]>;
+/// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
+class truncate_of_opcode<Instruction extOpcode> : GICombineRule <
+ (defs root:$root, build_fn_matchinfo:$matchinfo),
+ (match (extOpcode $ext, $src):$ExtMI,
+ (G_TRUNC $root, $ext):$root,
+ [{ return Helper.matchTruncateOfExt(*${root}, *${ExtMI}, ${matchinfo}); }]),
+ (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>;
+
+def truncate_of_zext : truncate_of_opcode<G_ZEXT>;
+def truncate_of_sext : truncate_of_opcode<G_SEXT>;
+def truncate_of_anyext : truncate_of_opcode<G_ANYEXT>;
+
+def cast_combines: GICombineGroup<[
+ truncate_of_zext,
+ truncate_of_sext,
+ truncate_of_anyext
+]>;
+
+
// FIXME: These should use the custom predicate feature once it lands.
def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
undef_to_negative_one,
@@ -1828,7 +1838,7 @@ def constant_fold_binops : GICombineGroup<[constant_fold_binop,
def prefer_sign_combines : GICombineGroup<[nneg_zext]>;
def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
- vector_ops_combines, freeze_combines,
+ vector_ops_combines, freeze_combines, cast_combines,
insert_vec_elt_combines, extract_vec_elt_combines, combines_for_extload,
combine_extracted_vector_load,
undef_combines, identity_combines, phi_combines,
@@ -1839,7 +1849,7 @@ def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
known_bits_simplifications, ext_ext_fold,
not_cmp_fold, opt_brcond_by_inverting_cond,
unmerge_merge, unmerge_cst, unmerge_dead_to_trunc,
- unmerge_zext_to_zext, merge_unmerge, trunc_ext_fold, trunc_shift,
+ unmerge_zext_to_zext, merge_unmerge, trunc_shift,
const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine,
div_rem_to_divrem, funnel_shift_combines, bitreverse_shift, commute_shift,
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 208f554eb8f98..8c05931812af5 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2582,40 +2582,6 @@ void CombinerHelper::applyCombineExtOfExt(
}
}
-bool CombinerHelper::matchCombineTruncOfExt(
- MachineInstr &MI, std::pair<Register, unsigned> &MatchInfo) {
- assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Expected a G_TRUNC");
- Register SrcReg = MI.getOperand(1).getReg();
- MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
- unsigned SrcOpc = SrcMI->getOpcode();
- if (SrcOpc == TargetOpcode::G_ANYEXT || SrcOpc == TargetOpcode::G_SEXT ||
- SrcOpc == TargetOpcode::G_ZEXT) {
- MatchInfo = std::make_pair(SrcMI->getOperand(1).getReg(), SrcOpc);
- return true;
- }
- return false;
-}
-
-void CombinerHelper::applyCombineTruncOfExt(
- MachineInstr &MI, std::pair<Register, unsigned> &MatchInfo) {
- assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Expected a G_TRUNC");
- Register SrcReg = MatchInfo.first;
- unsigned SrcExtOp = MatchInfo.second;
- Register DstReg = MI.getOperand(0).getReg();
- LLT SrcTy = MRI.getType(SrcReg);
- LLT DstTy = MRI.getType(DstReg);
- if (SrcTy == DstTy) {
- MI.eraseFromParent();
- replaceRegWith(MRI, DstReg, SrcReg);
- return;
- }
- if (SrcTy.getSizeInBits() < DstTy.getSizeInBits())
- Builder.buildInstr(SrcExtOp, {DstReg}, {SrcReg});
- else
- Builder.buildTrunc(DstReg, SrcReg);
- MI.eraseFromParent();
-}
-
static LLT getMidVTForTruncRightShiftCombine(LLT ShiftTy, LLT TruncTy) {
const unsigned ShiftSize = ShiftTy.getScalarSizeInBits();
const unsigned TruncSize = TruncTy.getScalarSizeInBits();
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
index 8fe69f21fafd1..f11eb512249df 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
@@ -113,3 +113,45 @@ bool CombinerHelper::matchNonNegZext(const MachineOperand &MO,
return false;
}
+
+bool CombinerHelper::matchTruncateOfExt(const MachineInstr &Root,
+ const MachineInstr &ExtMI,
+ BuildFnTy &MatchInfo) {
+ const GTrunc *Trunc = cast<GTrunc>(&Root);
+ const GExtOp *Ext = cast<GExtOp>(&ExtMI);
+
+ if (!MRI.hasOneNonDBGUse(Ext->getReg(0)))
+ return false;
+
+ Register Dst = Trunc->getReg(0);
+ Register Src = Ext->getSrcReg();
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+
+ if (SrcTy == DstTy) {
+ // The source and the destination are equally sized. We need to copy.
+ MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); };
+
+ return true;
+ } else if (SrcTy.getScalarSizeInBits() < DstTy.getScalarSizeInBits()) {
+ // Protect against scalable vectors.
+ if (!isLegalOrBeforeLegalizer({Ext->getOpcode(), {DstTy, SrcTy}}))
+ return false;
+
+ // If the source is smaller than the destination, we need to extend.
+ MatchInfo = [=](MachineIRBuilder &B) {
+ B.buildInstr(Ext->getOpcode(), {Dst}, {Src});
+ };
+
+ return true;
+ }
+
+ // The source is larger than the destination. We need to truncate.
+
+ if (!isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}}))
+ return false;
+
+ MatchInfo = [=](MachineIRBuilder &B) { B.buildTrunc(Dst, Src); };
+
+ return true;
+}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index b619aac709d98..de3f323891a36 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -2659,9 +2659,9 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) {
; CHECK-NOLSE-O1-NEXT: LBB35_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldaxrb w8, [x0]
-; CHECK-NOLSE-O1-NEXT: and w10, w8, #0xff
-; CHECK-NOLSE-O1-NEXT: cmp w10, w9
-; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, lo
+; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xff
+; CHECK-NOLSE-O1-NEXT: cmp w8, w9
+; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, lo
; CHECK-NOLSE-O1-NEXT: stlxrb w11, w10, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB35_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2674,9 +2674,9 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) {
; CHECK-OUTLINE-O1-NEXT: LBB35_1: ; %atomicrmw.start
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O1-NEXT: ldaxrb w8, [x0]
-; CHECK-OUTLINE-O1-NEXT: and w10, w8, #0xff
-; CHECK-OUTLINE-O1-NEXT: cmp w10, w9
-; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, lo
+; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xff
+; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
+; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, lo
; CHECK-OUTLINE-O1-NEXT: stlxrb w11, w10, [x0]
; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB35_1
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2781,9 +2781,9 @@ define i8 @atomicrmw_umax_i8(ptr %ptr, i8 %rhs) {
; CHECK-NOLSE-O1-NEXT: LBB36_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldxrb w8, [x0]
-; CHECK-NOLSE-O1-NEXT: and w10, w8, #0xff
-; CHECK-NOLSE-O1-NEXT: cmp w10, w9
-; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, hi
+; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xff
+; CHECK-NOLSE-O1-NEXT: cmp w8, w9
+; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, hi
; CHECK-NOLSE-O1-NEXT: stxrb w11, w10, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB36_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2796,9 +2796,9 @@ define i8 @atomicrmw_umax_i8(ptr %ptr, i8 %rhs) {
; CHECK-OUTLINE-O1-NEXT: LBB36_1: ; %atomicrmw.start
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O1-NEXT: ldxrb w8, [x0]
-; CHECK-OUTLINE-O1-NEXT: and w10, w8, #0xff
-; CHECK-OUTLINE-O1-NEXT: cmp w10, w9
-; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, hi
+; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xff
+; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
+; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, hi
; CHECK-OUTLINE-O1-NEXT: stxrb w11, w10, [x0]
; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB36_1
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3714,9 +3714,9 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O1-NEXT: LBB45_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldaxrh w8, [x0]
-; CHECK-NOLSE-O1-NEXT: and w10, w8, #0xffff
-; CHECK-NOLSE-O1-NEXT: cmp w10, w9
-; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, lo
+; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xffff
+; CHECK-NOLSE-O1-NEXT: cmp w8, w9
+; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, lo
; CHECK-NOLSE-O1-NEXT: stlxrh w11, w10, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB45_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3729,9 +3729,9 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O1-NEXT: LBB45_1: ; %atomicrmw.start
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O1-NEXT: ldaxrh w8, [x0]
-; CHECK-OUTLINE-O1-NEXT: and w10, w8, #0xffff
-; CHECK-OUTLINE-O1-NEXT: cmp w10, w9
-; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, lo
+; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xffff
+; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
+; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, lo
; CHECK-OUTLINE-O1-NEXT: stlxrh w11, w10, [x0]
; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB45_1
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3836,9 +3836,9 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-NOLSE-O1-NEXT: LBB46_1: ; %atomicrmw.start
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O1-NEXT: ldxrh w8, [x0]
-; CHECK-NOLSE-O1-NEXT: and w10, w8, #0xffff
-; CHECK-NOLSE-O1-NEXT: cmp w10, w9
-; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, hi
+; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xffff
+; CHECK-NOLSE-O1-NEXT: cmp w8, w9
+; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, hi
; CHECK-NOLSE-O1-NEXT: stxrh w11, w10, [x0]
; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB46_1
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3851,9 +3851,9 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-OUTLINE-O1-NEXT: LBB46_1: ; %atomicrmw.start
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-OUTLINE-O1-NEXT: ldxrh w8, [x0]
-; CHECK-OUTLINE-O1-NEXT: and w10, w8, #0xffff
-; CHECK-OUTLINE-O1-NEXT: cmp w10, w9
-; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, hi
+; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xffff
+; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
+; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, hi
; CHECK-OUTLINE-O1-NEXT: stxrh w11, w10, [x0]
; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB46_1
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
index c8d313cf31afd..c6819ff39ed33 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
@@ -926,16 +926,16 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
- ; CHECK-NEXT: renamable $w10 = ANDWri renamable $w8, 7
- ; CHECK-NEXT: $wzr = SUBSWrs renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
+ ; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 7, implicit killed $x8
+ ; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
+ ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
; CHECK-NEXT: early-clobber renamable $w11 = STLXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
- ; CHECK-NEXT: liveins: $x8
+ ; CHECK-NEXT: liveins: $w8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
+ ; CHECK-NEXT: $w0 = ORRWrs $wzr, killed $w8, 0
; CHECK-NEXT: RET undef $lr, implicit $w0
%res = atomicrmw umin ptr %ptr, i8 %rhs seq_cst, !pcsections !0
ret i8 %res
@@ -954,16 +954,16 @@ define i8 @atomicrmw_umax_i8(ptr %ptr, i8 %rhs) {
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
- ; CHECK-NEXT: renamable $w10 = ANDWri renamable $w8, 7
- ; CHECK-NEXT: $wzr = SUBSWrs renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
+ ; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 7, implicit killed $x8
+ ; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
+ ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
; CHECK-NEXT: early-clobber renamable $w11 = STXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s8) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
- ; CHECK-NEXT: liveins: $x8
+ ; CHECK-NEXT: liveins: $w8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
+ ; CHECK-NEXT: $w0 = ORRWrs $wzr, killed $w8, 0
; CHECK-NEXT: RET undef $lr, implicit $w0
%res = atomicrmw umax ptr %ptr, i8 %rhs monotonic, !pcsections !0
ret i8 %res
@@ -1179,16 +1179,16 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
- ; CHECK-NEXT: renamable $w10 = ANDWri renamable $w8, 15
- ; CHECK-NEXT: $wzr = SUBSWrs renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
+ ; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 15, implicit killed $x8
+ ; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
+ ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
; CHECK-NEXT: early-clobber renamable $w11 = STLXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
- ; CHECK-NEXT: liveins: $x8
+ ; CHECK-NEXT: liveins: $w8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
+ ; CHECK-NEXT: $w0 = ORRWrs $wzr, killed $w8, 0
; CHECK-NEXT: RET undef $lr, implicit $w0
%res = atomicrmw umin ptr %ptr, i16 %rhs seq_cst, !pcsections !0
ret i16 %res
@@ -1207,16 +1207,16 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
; CHECK-NEXT: liveins: $w9, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
- ; CHECK-NEXT: renamable $w10 = ANDWri renamable $w8, 15
- ; CHECK-NEXT: $wzr = SUBSWrs renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0
- ; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
+ ; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 15, implicit killed $x8
+ ; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
+ ; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
; CHECK-NEXT: early-clobber renamable $w11 = STXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s16) into %ir.ptr)
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.atomicrmw.end:
- ; CHECK-NEXT: liveins: $x8
+ ; CHECK-NEXT: liveins: $w8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
+ ; CHECK-NEXT: $w0 = ORRWrs $wzr, killed $w8, 0
; CHECK-NEXT: RET undef $lr, implicit $w0
%res = atomicrmw umax ptr %ptr, i16 %rhs monotonic, !pcsections !0
ret i16 %res
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
index 9f1d403340f49..4a38b5d4c63dd 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-trunc.mir
@@ -1,36 +1,51 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK,CHECK-PRE
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s | FileCheck %s --check-prefixes=CHECK,CHECK-POST
+
---
name: test_combine_trunc_undef
+legalized: true
body: |
bb.1:
; CHECK-LABEL: name: test_combine_trunc_undef
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: $w0 = COPY [[DEF]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
%0:_(s64) = G_IMPLICIT_DEF
%1:_(s32) = G_TRUNC %0(s64)
$w0 = COPY %1(s32)
...
---
name: test_combine_trunc_undef_vec
+legalized: true
body: |
bb.1:
; CHECK-LABEL: name: test_combine_trunc_undef_vec
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
- ; CHECK: $x0 = COPY [[DEF]](<2 x s32>)
+ ; CHECK-NEXT: $x0 = COPY [[DEF]](<2 x s32>)
%0:_(<2 x s64>) = G_IMPLICIT_DEF
%1:_(<2 x s32>) = G_TRUNC %0(<2 x s64>)
$x0 = COPY %1(<2 x s32>)
...
---
name: test_combine_trunc_anyext_s32_s16
+legalized: true
body: |
bb.1:
liveins: $h0
- ; CHECK-LABEL: name: test_combine_trunc_anyext_s32_s16
- ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
- ; CHECK: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK-PRE-LABEL: name: test_combine_trunc_anyext_s32_s16
+ ; CHECK-PRE: liveins: $h0
+ ; CHECK-PRE-NEXT: {{ $}}
+ ; CHECK-PRE-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+ ; CHECK-PRE-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
+ ; CHECK-PRE-NEXT: $w0 = COPY [[ANYEXT]](s32)
+ ;
+ ; CHECK-POST-LABEL: name: test_combine_trunc_anyext_s32_s16
+ ; CHECK-POST: liveins: $h0
+ ; CHECK-POST-NEXT: {{ $}}
+ ; CHECK-POST-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+ ; CHECK-POST-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s16)
+ ; CHECK-POST-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ANYEXT]](s64)
+ ; CHECK-POST-NEXT: $w0 = COPY [[TRUNC]](s32)
%0:_(s16) = COPY $h0
%1:_(s64) = G_ANYEXT %0(s16)
%2:_(s32) = G_TRUNC %1(s64)
@@ -38,13 +53,24 @@ body: |
...
---
name: test_combine_trunc_anyext_s32_s16_vec
+legalized: true
body: |
bb.1:
liveins: $s0
- ; CHECK-LABEL: name: test_combine_trunc_anyext_s32_s16_vec
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[COPY]](<2 x s16>)
- ; CHECK: $x0 = COPY [[ANYEXT]](<2 x s32>)
+ ; CHECK-PRE-LABEL: name: test_combine_trunc_anyext_s32_s16_vec
+ ; CHECK-PRE: liveins: $s0
+ ; CHECK-PRE-NEXT: {{ $}}
+ ; CHECK-PRE-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
+ ; CHECK-PRE-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[COPY]](<2 x s16>)
+ ; CHECK-PRE-NEXT: $x0 = COPY [[ANYEXT]](<2 x s32>)
+ ;
+ ; CHECK-POST-LABEL: name: test_combine_trunc_anyext_s32_s16_vec
+ ; CHECK-POST: liveins: $s0
+ ; CHECK-POST-NEXT: {{ $}}
+ ; CHECK-POST-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $s0
+ ; CHECK-POST-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[COPY]](<2 x s16>)
+ ; CHECK-POST-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ANYEXT]](<2 x s64>)
+ ; CHECK-POST-NEXT: $x0 = COPY [[TRUNC]](<2 x s32>)
%0:_(<2 x s16>) = COPY $s0
%1:_(<2 x s64>) = G_ANYEXT %0(<2 x s16>)
%2:_(<2 x s32>) = G_TRUNC %1(<2 x s64>)
@@ -52,13 +78,24 @@ body: |
...
---
name: test_combine_trunc_sext_s32_s16
+legalized: true
body: |
bb.1:
liveins: $h0
- ; CHECK-LABEL: name: test_combine_trunc_sext_s32_s16
- ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
- ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
- ; CHECK: $w0 = COPY [[SEXT]](s32)
+ ; CHECK-PRE-LABEL: name: test_combine_trunc_sext_s32_s16
+ ; CHECK-PRE: liveins: $h0
+ ; CHECK-PRE-NEXT: {{ $}}
+ ; CHECK-PRE-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+ ; CHECK-PRE-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
+ ; CHECK-PRE-NEXT: $w0 = COPY [[SEXT]](s32)
+ ;
+ ; CHECK-POST-LABEL: name: test_combine_trunc_sext_s32_s16
+ ; CHECK-POST: liveins: $h0
+ ; CHECK-POST-NEXT: {{ $}}
+ ; CHECK-POST-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+ ; CHECK-POST-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
+ ; CHECK-POST-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT]](s64)
+ ; CHECK-POST-NEXT: $w0 = COPY [[TRUNC]](s32)
%0:_(s16) = COPY $h0
%1:_(s64) = G_SEXT %0(s16)
%2:_(s32) = G_TRUNC %1(s64)
@@ -66,13 +103,24 @@ body: |
...
---
name: test_combine_trunc_zext_s32_s16
+legalized: true
body: |
bb.1:
liveins: $h0
- ; CHECK-LABEL: name: test_combine_trunc_zext_s32_s16
- ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
- ; CHECK: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK-PRE-LABEL: name: test_combine_trunc_zext_s32_s16
+ ; CHECK-PRE: liveins: $h0
+ ; CHECK-PRE-NEXT: {{ $}}
+ ; CHECK-PRE-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+ ; CHECK-PRE-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
+ ; CHECK-PRE-NEXT: $w0 = COPY [[ZEXT]](s32)
+ ;
+ ; CHECK-POST-LABEL: name: test_combine_trunc_zext_s32_s16
+ ; CHECK-POST: liveins: $h0
+ ; CHECK-POST-NEXT: {{ $}}
+ ; CHECK-POST-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+ ; CHECK-POST-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s16)
+ ; CHECK-POST-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ZEXT]](s64)
+ ; CHECK-POST-NEXT: $w0 = COPY [[TRUNC]](s32)
%0:_(s16) = COPY $h0
%1:_(s64) = G_ZEXT %0(s16)
%2:_(s32) = G_TRUNC %1(s64)
@@ -80,12 +128,23 @@ body: |
...
---
name: test_combine_trunc_anyext_s32_s32
+legalized: true
body: |
bb.1:
liveins: $w0
- ; CHECK-LABEL: name: test_combine_trunc_anyext_s32_s32
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: $w0 = COPY [[COPY]](s32)
+ ; CHECK-PRE-LABEL: name: test_combine_trunc_anyext_s32_s32
+ ; CHECK-PRE: liveins: $w0
+ ; CHECK-PRE-NEXT: {{ $}}
+ ; CHECK-PRE-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-PRE-NEXT: $w0 = COPY [[COPY]](s32)
+ ;
+ ; CHECK-POST-LABEL: name: test_combine_trunc_anyext_s32_s32
+ ; CHECK-POST: liveins: $w0
+ ; CHECK-POST-NEXT: {{ $}}
+ ; CHECK-POST-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-POST-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
+ ; CHECK-POST-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ANYEXT]](s64)
+ ; CHECK-POST-NEXT: $w0 = COPY [[TRUNC]](s32)
%0:_(s32) = COPY $w0
%1:_(s64) = G_ANYEXT %0(s32)
%2:_(s32) = G_TRUNC %1(s64)
@@ -93,13 +152,24 @@ body: |
...
---
name: test_combine_trunc_anyext_s32_s64
+legalized: true
body: |
bb.1:
liveins: $x0
- ; CHECK-LABEL: name: test_combine_trunc_anyext_s32_s64
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-PRE-LABEL: name: test_combine_trunc_anyext_s32_s64
+ ; CHECK-PRE: liveins: $x0
+ ; CHECK-PRE-NEXT: {{ $}}
+ ; CHECK-PRE-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-PRE-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-PRE-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ;
+ ; CHECK-POST-LABEL: name: test_combine_trunc_anyext_s32_s64
+ ; CHECK-POST: liveins: $x0
+ ; CHECK-POST-NEXT: {{ $}}
+ ; CHECK-POST-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-POST-NEXT: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[COPY]](s64)
+ ; CHECK-POST-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ANYEXT]](s128)
+ ; CHECK-POST-NEXT: $w0 = COPY [[TRUNC]](s32)
%0:_(s64) = COPY $x0
%1:_(s128) = G_ANYEXT %0(s64)
%2:_(s32) = G_TRUNC %1(s128)
@@ -107,15 +177,27 @@ body: |
...
---
name: test_combine_trunc_shl_s32_by_2
+legalized: true
body: |
bb.1:
liveins: $w0
- ; CHECK-LABEL: name: test_combine_trunc_shl_s32_by_2
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s32)
- ; CHECK: $h0 = COPY [[SHL]](s16)
+ ; CHECK-PRE-LABEL: name: test_combine_trunc_shl_s32_by_2
+ ; CHECK-PRE: liveins: $w0
+ ; CHECK-PRE-NEXT: {{ $}}
+ ; CHECK-PRE-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-PRE-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-PRE-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK-PRE-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s32)
+ ; CHECK-PRE-NEXT: $h0 = COPY [[SHL]](s16)
+ ;
+ ; CHECK-POST-LABEL: name: test_combine_trunc_shl_s32_by_2
+ ; CHECK-POST: liveins: $w0
+ ; CHECK-POST-NEXT: {{ $}}
+ ; CHECK-POST-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-POST-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK-POST-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-POST-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+ ; CHECK-POST-NEXT: $h0 = COPY [[TRUNC]](s16)
%0:_(s32) = COPY $w0
%1:_(s32) = G_CONSTANT i32 2
%2:_(s32) = G_SHL %0(s32), %1(s32)
@@ -124,18 +206,41 @@ body: |
...
---
name: test_combine_trunc_shl_s32_by_17
+legalized: true
body: |
bb.1:
liveins: $w0
; CHECK-LABEL: name: test_combine_trunc_shl_s32_by_17
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; CHECK: $h0 = COPY [[TRUNC]](s16)
+ ; CHECK: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+ ; CHECK-NEXT: $h0 = COPY [[TRUNC]](s16)
%0:_(s32) = COPY $w0
%1:_(s32) = G_CONSTANT i32 17
%2:_(s32) = G_SHL %0(s32), %1(s32)
%3:_(s16) = G_TRUNC %2(s32)
$h0 = COPY %3(s16)
...
+---
+name: test_combine_trunc_multi_use
+legalized: true
+body: |
+ bb.1:
+ liveins: $w0
+ ; CHECK-LABEL: name: test_combine_trunc_multi_use
+ ; CHECK: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ZEXT]](s64)
+ ; CHECK-NEXT: $h0 = COPY [[TRUNC]](s16)
+ ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64)
+ %0:_(s32) = COPY $w0
+ %2:_(s64) = G_ZEXT %0(s32)
+ %3:_(s16) = G_TRUNC %2(s64)
+ $h0 = COPY %3(s16)
+ $x0 = COPY %2(s64)
+...
>From db776056167a4dbfd134bb362fc61b148056c55f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Wed, 24 Jul 2024 14:29:23 +0200
Subject: [PATCH 2/3] address review comments
---
.../GlobalISel/CombinerHelperCasts.cpp | 22 ++++++++++++-------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
index f11eb512249df..360a4811bca81 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
@@ -133,12 +133,14 @@ bool CombinerHelper::matchTruncateOfExt(const MachineInstr &Root,
MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); };
return true;
- } else if (SrcTy.getScalarSizeInBits() < DstTy.getScalarSizeInBits()) {
- // Protect against scalable vectors.
+ }
+
+ if (SrcTy.getScalarSizeInBits() < DstTy.getScalarSizeInBits()) {
+ // If the source is smaller than the destination, we need to extend.
+
if (!isLegalOrBeforeLegalizer({Ext->getOpcode(), {DstTy, SrcTy}}))
return false;
- // If the source is smaller than the destination, we need to extend.
MatchInfo = [=](MachineIRBuilder &B) {
B.buildInstr(Ext->getOpcode(), {Dst}, {Src});
};
@@ -146,12 +148,16 @@ bool CombinerHelper::matchTruncateOfExt(const MachineInstr &Root,
return true;
}
- // The source is larger than the destination. We need to truncate.
+ if (SrcTy.getScalarSizeInBits() > DstTy.getScalarSizeInBits()) {
+ // The source is larger than the destination. We need to truncate.
- if (!isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}}))
- return false;
+ if (!isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}}))
+ return false;
- MatchInfo = [=](MachineIRBuilder &B) { B.buildTrunc(Dst, Src); };
+ MatchInfo = [=](MachineIRBuilder &B) { B.buildTrunc(Dst, Src); };
- return true;
+ return true;
+ }
+
+ return false;
}
>From e8b5efe16cc7f86f5d2512b0fea735566e88ac6f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Wed, 24 Jul 2024 15:50:38 +0200
Subject: [PATCH 3/3] ping ci
---
llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
index 360a4811bca81..1e0deeef4f686 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
@@ -149,7 +149,7 @@ bool CombinerHelper::matchTruncateOfExt(const MachineInstr &Root,
}
if (SrcTy.getScalarSizeInBits() > DstTy.getScalarSizeInBits()) {
- // The source is larger than the destination. We need to truncate.
+ // If the source is larger than the destination, we need to truncate.
if (!isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}}))
return false;
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