[llvm] [MachineLoopInfo] Fix assertion failure on undef use operands (PR #100137)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 24 02:10:37 PDT 2024
https://github.com/jayfoad updated https://github.com/llvm/llvm-project/pull/100137
>From 53398d6fd99a6ed49d72723b35c08a33a86b2c51 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Tue, 23 Jul 2024 15:56:48 +0100
Subject: [PATCH 1/6] [MachineLoopInfo] Fix assertion failure on undef use
operands
Fixes #100115
---
llvm/lib/CodeGen/MachineLoopInfo.cpp | 2 +-
llvm/test/CodeGen/AMDGPU/dpp64_combine.ll | 25 +++++++++++++++++++++--
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineLoopInfo.cpp b/llvm/lib/CodeGen/MachineLoopInfo.cpp
index a03c008e6045a..88ba10fbe29a9 100644
--- a/llvm/lib/CodeGen/MachineLoopInfo.cpp
+++ b/llvm/lib/CodeGen/MachineLoopInfo.cpp
@@ -287,7 +287,7 @@ bool MachineLoop::isLoopInvariant(MachineInstr &I,
}
}
- if (!MO.isUse())
+ if (!MO.readsReg())
continue;
assert(MRI->getVRegDef(Reg) &&
diff --git a/llvm/test/CodeGen/AMDGPU/dpp64_combine.ll b/llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
index b4218bc2afc7f..3d8cda589f46f 100644
--- a/llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/dpp64_combine.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP64,GFX90A
; RUN: llc -mtriple=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP64,DPPMOV64
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS,GFX10
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10PLUS,GFX11
; GCN-LABEL: {{^}}dpp64_ceil:
; GCN: global_load_{{dwordx2|b64}} [[V:v\[[0-9:]+\]]],
@@ -69,6 +69,27 @@ define amdgpu_kernel void @dpp64_div(ptr addrspace(1) %arg, i64 %in1) {
ret void
}
+; GCN-LABEL: {{^}}dpp64_loop:
+; GCN: v_mov_b32_dpp
+; DPP64: v_mov_b32_dpp
+; GFX90A: v_add_co_u32_e32
+; GFX90A: v_addc_co_u32_e32
+; DPPMOV64: v_lshl_add_u64
+; GFX10: v_mov_b32_dpp
+; GFX10: v_add_co_u32
+; GFX10: v_add_co_ci_u32_e32
+; GFX11: v_add_co_u32_e64_dpp
+; GFX11: v_add_co_ci_u32_e32
+define amdgpu_cs void @dpp64_loop(i64 %arg) {
+bb:
+ br label %bb1
+bb1:
+ %i = call i64 @llvm.amdgcn.update.dpp.i64(i64 0, i64 0, i32 0, i32 0, i32 0, i1 false)
+ %i2 = add i64 %i, %arg
+ %i3 = atomicrmw add ptr addrspace(1) null, i64 %i2 monotonic, align 8
+ br label %bb1
+}
+
declare i32 @llvm.amdgcn.workitem.id.x()
declare i64 @llvm.amdgcn.update.dpp.i64(i64, i64, i32, i32, i32, i1) #0
declare double @llvm.ceil.f64(double)
>From 21f6367c4efc010f0bc613714328596588420be9 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Tue, 23 Jul 2024 16:35:37 +0100
Subject: [PATCH 2/6] Add MIR test
---
.../test/CodeGen/AMDGPU/machinelicm-crash.mir | 77 +++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/machinelicm-crash.mir
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-crash.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-crash.mir
new file mode 100644
index 0000000000000..dbab6209eedeb
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-crash.mir
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=early-machinelicm %s | FileCheck %s
+
+---
+name: f
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: f
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.3(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, undef [[DEF]], %subreg.sub1
+ ; CHECK-NEXT: S_BRANCH %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.5(0x04000000), %bb.1(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $vcc_lo = COPY undef [[DEF1]]
+ ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.5, implicit $vcc_lo
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit undef $scc
+ ; CHECK-NEXT: S_BRANCH %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: SI_LOOP undef [[DEF1]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5:
+ ; CHECK-NEXT: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x80000000)
+ liveins: $vgpr0, $vgpr1
+
+ %59:vgpr_32 = IMPLICIT_DEF
+ %60:sreg_32 = IMPLICIT_DEF
+
+ bb.1:
+ successors: %bb.3(0x80000000)
+
+ %16:vreg_64 = REG_SEQUENCE undef %52:vgpr_32, %subreg.sub0, undef %59, %subreg.sub1
+ S_BRANCH %bb.3
+
+ bb.2:
+ successors: %bb.5(0x04000000), %bb.1(0x7c000000)
+
+ $vcc_lo = COPY undef %60
+ S_CBRANCH_VCCNZ %bb.5, implicit $vcc
+ S_BRANCH %bb.1
+
+ bb.3:
+ successors: %bb.4(0x04000000), %bb.3(0x7c000000)
+
+ S_CBRANCH_SCC1 %bb.3, implicit undef $scc
+ S_BRANCH %bb.4
+
+ bb.4:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+
+ SI_LOOP undef %60, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ S_BRANCH %bb.2
+
+ bb.5:
+ S_ENDPGM 0
+...
>From 4f059b6dc5802a8c383db184ea444a1ac437d5e1 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 24 Jul 2024 09:57:56 +0100
Subject: [PATCH 3/6] Compact register numbers
---
llvm/test/CodeGen/AMDGPU/machinelicm-crash.mir | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-crash.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-crash.mir
index dbab6209eedeb..c4017f32f1c4b 100644
--- a/llvm/test/CodeGen/AMDGPU/machinelicm-crash.mir
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-crash.mir
@@ -44,19 +44,19 @@ body: |
successors: %bb.1(0x80000000)
liveins: $vgpr0, $vgpr1
- %59:vgpr_32 = IMPLICIT_DEF
- %60:sreg_32 = IMPLICIT_DEF
+ %0:vgpr_32 = IMPLICIT_DEF
+ %1:sreg_32 = IMPLICIT_DEF
bb.1:
successors: %bb.3(0x80000000)
- %16:vreg_64 = REG_SEQUENCE undef %52:vgpr_32, %subreg.sub0, undef %59, %subreg.sub1
+ %2:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, undef %0, %subreg.sub1
S_BRANCH %bb.3
bb.2:
successors: %bb.5(0x04000000), %bb.1(0x7c000000)
- $vcc_lo = COPY undef %60
+ $vcc_lo = COPY undef %1
S_CBRANCH_VCCNZ %bb.5, implicit $vcc
S_BRANCH %bb.1
@@ -69,7 +69,7 @@ body: |
bb.4:
successors: %bb.2(0x40000000), %bb.1(0x40000000)
- SI_LOOP undef %60, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ SI_LOOP undef %1, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
S_BRANCH %bb.2
bb.5:
>From b5b16cf8f89d253b473c7f7fa78e89665404c43f Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 24 Jul 2024 10:00:08 +0100
Subject: [PATCH 4/6] Rename test file
---
.../AMDGPU/{machinelicm-crash.mir => machinelicm-undef-use.mir} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename llvm/test/CodeGen/AMDGPU/{machinelicm-crash.mir => machinelicm-undef-use.mir} (100%)
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-crash.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
similarity index 100%
rename from llvm/test/CodeGen/AMDGPU/machinelicm-crash.mir
rename to llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
>From 1b85e26203e0e567eeea207c81bd025953546c24 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 24 Jul 2024 10:02:30 +0100
Subject: [PATCH 5/6] Add comments. Improve function name.
---
llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
index c4017f32f1c4b..eceba15067ec2 100644
--- a/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
@@ -1,11 +1,13 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=early-machinelicm %s | FileCheck %s
+# Issue #100115: test that MachineLICM does not assert on the undef use operand
+# of the REG_SEQUENCE instruction.
---
-name: f
+name: test_undef_use
tracksRegLiveness: true
body: |
- ; CHECK-LABEL: name: f
+ ; CHECK-LABEL: name: test_undef_use
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
>From f2f2452c9b2fbedecc050c30451dcaeb06c6512f Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 24 Jul 2024 10:10:21 +0100
Subject: [PATCH 6/6] Fix RUN line
---
llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir b/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
index eceba15067ec2..07eaa9f95604d 100644
--- a/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/machinelicm-undef-use.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=early-machinelicm %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=early-machinelicm %s -o - | FileCheck %s
# Issue #100115: test that MachineLICM does not assert on the undef use operand
# of the REG_SEQUENCE instruction.
More information about the llvm-commits
mailing list