[llvm] [RISCV] Add unit strided load/store to whole register peephole (PR #100116)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 23 20:47:28 PDT 2024
https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/100116
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