[llvm] [GlobalIsel][NFC] move cast code (PR #100196)
Thorsten Schütt via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 23 13:27:55 PDT 2024
https://github.com/tschuett created https://github.com/llvm/llvm-project/pull/100196
Preparation for more cast combines
>From ddb96a7ead3ecff11726520bb97a523fdc56c349 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= <schuett at gmail.com>
Date: Fri, 12 Jul 2024 10:52:59 +0200
Subject: [PATCH] [GlobalIsel][NFC] move cast code
Preparation for more cast combines
---
llvm/lib/CodeGen/GlobalISel/CMakeLists.txt | 1 +
.../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 89 --------------
.../GlobalISel/CombinerHelperCasts.cpp | 115 ++++++++++++++++++
3 files changed, 116 insertions(+), 89 deletions(-)
create mode 100644 llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
diff --git a/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt b/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt
index 54ac7f72011a6..a15b76440364b 100644
--- a/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt
+++ b/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt
@@ -6,6 +6,7 @@ add_llvm_component_library(LLVMGlobalISel
GlobalISel.cpp
Combiner.cpp
CombinerHelper.cpp
+ CombinerHelperCasts.cpp
CombinerHelperVectorOps.cpp
GIMatchTableExecutor.cpp
GISelChangeObserver.cpp
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index e77ea3e76ad71..208f554eb8f98 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -7457,92 +7457,3 @@ void CombinerHelper::applyExpandFPowI(MachineInstr &MI, int64_t Exponent) {
Builder.buildCopy(Dst, *Res);
MI.eraseFromParent();
}
-
-bool CombinerHelper::matchSextOfTrunc(const MachineOperand &MO,
- BuildFnTy &MatchInfo) {
- GSext *Sext = cast<GSext>(getDefIgnoringCopies(MO.getReg(), MRI));
- GTrunc *Trunc = cast<GTrunc>(getDefIgnoringCopies(Sext->getSrcReg(), MRI));
-
- Register Dst = Sext->getReg(0);
- Register Src = Trunc->getSrcReg();
-
- LLT DstTy = MRI.getType(Dst);
- LLT SrcTy = MRI.getType(Src);
-
- if (DstTy == SrcTy) {
- MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); };
- return true;
- }
-
- if (DstTy.getScalarSizeInBits() < SrcTy.getScalarSizeInBits() &&
- isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}})) {
- MatchInfo = [=](MachineIRBuilder &B) {
- B.buildTrunc(Dst, Src, MachineInstr::MIFlag::NoSWrap);
- };
- return true;
- }
-
- if (DstTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits() &&
- isLegalOrBeforeLegalizer({TargetOpcode::G_SEXT, {DstTy, SrcTy}})) {
- MatchInfo = [=](MachineIRBuilder &B) { B.buildSExt(Dst, Src); };
- return true;
- }
-
- return false;
-}
-
-bool CombinerHelper::matchZextOfTrunc(const MachineOperand &MO,
- BuildFnTy &MatchInfo) {
- GZext *Zext = cast<GZext>(getDefIgnoringCopies(MO.getReg(), MRI));
- GTrunc *Trunc = cast<GTrunc>(getDefIgnoringCopies(Zext->getSrcReg(), MRI));
-
- Register Dst = Zext->getReg(0);
- Register Src = Trunc->getSrcReg();
-
- LLT DstTy = MRI.getType(Dst);
- LLT SrcTy = MRI.getType(Src);
-
- if (DstTy == SrcTy) {
- MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); };
- return true;
- }
-
- if (DstTy.getScalarSizeInBits() < SrcTy.getScalarSizeInBits() &&
- isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}})) {
- MatchInfo = [=](MachineIRBuilder &B) {
- B.buildTrunc(Dst, Src, MachineInstr::MIFlag::NoUWrap);
- };
- return true;
- }
-
- if (DstTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits() &&
- isLegalOrBeforeLegalizer({TargetOpcode::G_ZEXT, {DstTy, SrcTy}})) {
- MatchInfo = [=](MachineIRBuilder &B) {
- B.buildZExt(Dst, Src, MachineInstr::MIFlag::NonNeg);
- };
- return true;
- }
-
- return false;
-}
-
-bool CombinerHelper::matchNonNegZext(const MachineOperand &MO,
- BuildFnTy &MatchInfo) {
- GZext *Zext = cast<GZext>(MRI.getVRegDef(MO.getReg()));
-
- Register Dst = Zext->getReg(0);
- Register Src = Zext->getSrcReg();
-
- LLT DstTy = MRI.getType(Dst);
- LLT SrcTy = MRI.getType(Src);
- const auto &TLI = getTargetLowering();
-
- // Convert zext nneg to sext if sext is the preferred form for the target.
- if (isLegalOrBeforeLegalizer({TargetOpcode::G_SEXT, {DstTy, SrcTy}}) &&
- TLI.isSExtCheaperThanZExt(getMVTForLLT(SrcTy), getMVTForLLT(DstTy))) {
- MatchInfo = [=](MachineIRBuilder &B) { B.buildSExt(Dst, Src); };
- return true;
- }
-
- return false;
-}
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
new file mode 100644
index 0000000000000..8fe69f21fafd1
--- /dev/null
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp
@@ -0,0 +1,115 @@
+//===- CombinerHelperCasts.cpp---------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements CombinerHelper for G_ANYEXT, G_SEXT, G_TRUNC, and
+// G_ZEXT
+//
+//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
+#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/GlobalISel/Utils.h"
+#include "llvm/CodeGen/LowLevelTypeUtils.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/Support/Casting.h"
+
+#define DEBUG_TYPE "gi-combiner"
+
+using namespace llvm;
+
+bool CombinerHelper::matchSextOfTrunc(const MachineOperand &MO,
+ BuildFnTy &MatchInfo) {
+ GSext *Sext = cast<GSext>(getDefIgnoringCopies(MO.getReg(), MRI));
+ GTrunc *Trunc = cast<GTrunc>(getDefIgnoringCopies(Sext->getSrcReg(), MRI));
+
+ Register Dst = Sext->getReg(0);
+ Register Src = Trunc->getSrcReg();
+
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+
+ if (DstTy == SrcTy) {
+ MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); };
+ return true;
+ }
+
+ if (DstTy.getScalarSizeInBits() < SrcTy.getScalarSizeInBits() &&
+ isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}})) {
+ MatchInfo = [=](MachineIRBuilder &B) {
+ B.buildTrunc(Dst, Src, MachineInstr::MIFlag::NoSWrap);
+ };
+ return true;
+ }
+
+ if (DstTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits() &&
+ isLegalOrBeforeLegalizer({TargetOpcode::G_SEXT, {DstTy, SrcTy}})) {
+ MatchInfo = [=](MachineIRBuilder &B) { B.buildSExt(Dst, Src); };
+ return true;
+ }
+
+ return false;
+}
+
+bool CombinerHelper::matchZextOfTrunc(const MachineOperand &MO,
+ BuildFnTy &MatchInfo) {
+ GZext *Zext = cast<GZext>(getDefIgnoringCopies(MO.getReg(), MRI));
+ GTrunc *Trunc = cast<GTrunc>(getDefIgnoringCopies(Zext->getSrcReg(), MRI));
+
+ Register Dst = Zext->getReg(0);
+ Register Src = Trunc->getSrcReg();
+
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+
+ if (DstTy == SrcTy) {
+ MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); };
+ return true;
+ }
+
+ if (DstTy.getScalarSizeInBits() < SrcTy.getScalarSizeInBits() &&
+ isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}})) {
+ MatchInfo = [=](MachineIRBuilder &B) {
+ B.buildTrunc(Dst, Src, MachineInstr::MIFlag::NoUWrap);
+ };
+ return true;
+ }
+
+ if (DstTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits() &&
+ isLegalOrBeforeLegalizer({TargetOpcode::G_ZEXT, {DstTy, SrcTy}})) {
+ MatchInfo = [=](MachineIRBuilder &B) {
+ B.buildZExt(Dst, Src, MachineInstr::MIFlag::NonNeg);
+ };
+ return true;
+ }
+
+ return false;
+}
+
+bool CombinerHelper::matchNonNegZext(const MachineOperand &MO,
+ BuildFnTy &MatchInfo) {
+ GZext *Zext = cast<GZext>(MRI.getVRegDef(MO.getReg()));
+
+ Register Dst = Zext->getReg(0);
+ Register Src = Zext->getSrcReg();
+
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+ const auto &TLI = getTargetLowering();
+
+ // Convert zext nneg to sext if sext is the preferred form for the target.
+ if (isLegalOrBeforeLegalizer({TargetOpcode::G_SEXT, {DstTy, SrcTy}}) &&
+ TLI.isSExtCheaperThanZExt(getMVTForLLT(SrcTy), getMVTForLLT(DstTy))) {
+ MatchInfo = [=](MachineIRBuilder &B) { B.buildSExt(Dst, Src); };
+ return true;
+ }
+
+ return false;
+}
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