[llvm] [RegisterCoalescer] Fix SUBREG_TO_REG handling in the RegisterCoalescer. (PR #96839)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,37 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple x86_64-unknown-unknown -x mir < %s \
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arsenm wrote:

```suggestion
# RUN: llc -mtriple x86_64-unknown-unknown %s \
```

https://github.com/llvm/llvm-project/pull/96839