[llvm] fc832d5 - [AMDGPU] Implement llvm.lround intrinsic lowering. (#98970)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 23 09:34:38 PDT 2024
Author: Sumanth Gundapaneni
Date: 2024-07-23T20:34:34+04:00
New Revision: fc832d5349e1066b2ce8cec72bcbc39b9770758b
URL: https://github.com/llvm/llvm-project/commit/fc832d5349e1066b2ce8cec72bcbc39b9770758b
DIFF: https://github.com/llvm/llvm-project/commit/fc832d5349e1066b2ce8cec72bcbc39b9770758b.diff
LOG: [AMDGPU] Implement llvm.lround intrinsic lowering. (#98970)
This patch enables the target-independent lowering of llvm.lround via
GlobalISel. For SelectionDAG, the instrinsic is custom lowered for
AMDGPU. In order to support vector floating point input for llvm.lround,
this patch extends the target independent APIs and provide support for
scalarizing. pr98950 is needed to let verifier allow vector floating
point types
Added:
llvm/test/CodeGen/AMDGPU/lround.ll
Modified:
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 644dbae8f93a5..6c7885c491f41 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3881,6 +3881,17 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return lowerFMad(MI);
case TargetOpcode::G_FFLOOR:
return lowerFFloor(MI);
+ case TargetOpcode::G_LROUND:
+ case TargetOpcode::G_LLROUND: {
+ Register DstReg = MI.getOperand(0).getReg();
+ Register SrcReg = MI.getOperand(1).getReg();
+ LLT SrcTy = MRI.getType(SrcReg);
+ auto Round = MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND, {SrcTy},
+ {SrcReg});
+ MIRBuilder.buildFPTOSI(DstReg, Round);
+ MI.eraseFromParent();
+ return Legalized;
+ }
case TargetOpcode::G_INTRINSIC_ROUND:
return lowerIntrinsicRound(MI);
case TargetOpcode::G_FRINT: {
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 7f5b46af01c62..3a39f6a4d2b4a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3439,6 +3439,16 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
case ISD::FP_TO_UINT_SAT:
Results.push_back(TLI.expandFP_TO_INT_SAT(Node, DAG));
break;
+ case ISD::LROUND:
+ case ISD::LLROUND: {
+ SDValue Arg = Node->getOperand(0);
+ EVT ArgVT = Arg.getValueType();
+ EVT ResVT = Node->getValueType(0);
+ SDLoc dl(Node);
+ SDValue RoundNode = DAG.getNode(ISD::FROUND, dl, ArgVT, Arg);
+ Results.push_back(DAG.getNode(ISD::FP_TO_SINT, dl, ResVT, RoundNode));
+ break;
+ }
case ISD::VAARG:
Results.push_back(DAG.expandVAArg(Node));
Results.push_back(Results[0].getValue(1));
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 2be7fc90a0e75..bc5fc9659469d 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -824,13 +824,16 @@ void TargetLoweringBase::initActions() {
Expand);
// These library functions default to expand.
- setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10,
- ISD::FEXP, ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR,
- ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC,
- ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT,
- ISD::FROUNDEVEN, ISD::FTAN, ISD::FACOS, ISD::FASIN,
- ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH},
- {MVT::f32, MVT::f64, MVT::f128}, Expand);
+ setOperationAction(
+ {ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP,
+ ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL,
+ ISD::FRINT, ISD::FTRUNC, ISD::LRINT, ISD::LLRINT, ISD::FROUNDEVEN,
+ ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
+ ISD::FSINH, ISD::FTANH},
+ {MVT::f32, MVT::f64, MVT::f128}, Expand);
+
+ setOperationAction({ISD::LROUND, ISD::LLROUND},
+ {MVT::f32, MVT::f64, MVT::f128}, LibCall);
setOperationAction({ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
ISD::FSINH, ISD::FTANH},
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 39ae7c96cf772..af0ffc8fc7d07 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -397,6 +397,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FLOG2, MVT::f32, Custom);
setOperationAction(ISD::FROUND, {MVT::f32, MVT::f64}, Custom);
+ setOperationAction({ISD::LROUND, ISD::LLROUND},
+ {MVT::f16, MVT::f32, MVT::f64}, Expand);
setOperationAction(
{ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 74e93b0620d26..7ed97b9c542c7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1131,6 +1131,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.scalarize(0)
.lower();
+ getActionDefinitionsBuilder({G_LROUND, G_LLROUND})
+ .clampScalar(0, S16, S64)
+ .scalarize(0)
+ .lower();
+
getActionDefinitionsBuilder(G_INTRINSIC_FPTRUNC_ROUND)
.customFor({S16, S32})
.scalarize(0)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1c1f9e68facc0..a650e3ab0a6b6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -849,8 +849,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
setOperationAction(ISD::FROUNDEVEN, MVT::f80, Expand);
setOperationAction(ISD::FMA, MVT::f80, Expand);
- setOperationAction(ISD::LROUND, MVT::f80, Expand);
- setOperationAction(ISD::LLROUND, MVT::f80, Expand);
+ setOperationAction(ISD::LROUND, MVT::f80, LibCall);
+ setOperationAction(ISD::LLROUND, MVT::f80, LibCall);
setOperationAction(ISD::LRINT, MVT::f80, Custom);
setOperationAction(ISD::LLRINT, MVT::f80, Custom);
diff --git a/llvm/test/CodeGen/AMDGPU/lround.ll b/llvm/test/CodeGen/AMDGPU/lround.ll
new file mode 100644
index 0000000000000..d45d83026013d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/lround.ll
@@ -0,0 +1,1036 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub --version 5
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11-GISEL %s
+
+declare float @llvm.round.f32(float)
+declare i32 @llvm.lround.i32.f32(float)
+declare i32 @llvm.lround.i32.f64(double)
+declare i64 @llvm.lround.i64.f32(float)
+declare i64 @llvm.lround.i64.f64(double)
+declare i64 @llvm.llround.i64.f32(float)
+declare half @llvm.round.f16(half)
+declare i32 @llvm.lround.i32.f16(half %arg)
+
+define float @intrinsic_fround(float %arg) {
+; GFX9-SDAG-LABEL: intrinsic_fround:
+; GFX9-SDAG: ; %bb.0: ; %entry
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX9-SDAG-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
+; GFX9-SDAG-NEXT: s_brev_b32 s4, -2
+; GFX9-SDAG-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX9-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: intrinsic_fround:
+; GFX9-GISEL: ; %bb.0: ; %entry
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX9-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v3, 1
+; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v3, v2
+; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: intrinsic_fround:
+; GFX10-SDAG: ; %bb.0: ; %entry
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX10-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX10-SDAG-NEXT: v_cmp_ge_f32_e64 s4, |v2|, 0.5
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s4
+; GFX10-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX10-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: intrinsic_fround:
+; GFX10-GISEL: ; %bb.0: ; %entry
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX10-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX10-GISEL-NEXT: v_cmp_ge_f32_e64 s4, |v2|, 0.5
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s4
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v2
+; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-LABEL: intrinsic_fround:
+; GFX11-SDAG: ; %bb.0: ; %entry
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX11-SDAG-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
+; GFX11-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: intrinsic_fround:
+; GFX11-GISEL: ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX11-GISEL-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %res = tail call float @llvm.round.f32(float %arg)
+ ret float %res
+}
+
+define i32 @intrinsic_lround_i32_f32(float %arg) {
+; GFX9-SDAG-LABEL: intrinsic_lround_i32_f32:
+; GFX9-SDAG: ; %bb.0: ; %entry
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX9-SDAG-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
+; GFX9-SDAG-NEXT: s_brev_b32 s4, -2
+; GFX9-SDAG-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX9-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: intrinsic_lround_i32_f32:
+; GFX9-GISEL: ; %bb.0: ; %entry
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX9-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v3, 1
+; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v3, v2
+; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX9-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: intrinsic_lround_i32_f32:
+; GFX10-SDAG: ; %bb.0: ; %entry
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX10-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX10-SDAG-NEXT: v_cmp_ge_f32_e64 s4, |v2|, 0.5
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s4
+; GFX10-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX10-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-SDAG-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: intrinsic_lround_i32_f32:
+; GFX10-GISEL: ; %bb.0: ; %entry
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX10-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX10-GISEL-NEXT: v_cmp_ge_f32_e64 s4, |v2|, 0.5
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s4
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v2
+; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-LABEL: intrinsic_lround_i32_f32:
+; GFX11-SDAG: ; %bb.0: ; %entry
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX11-SDAG-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
+; GFX11-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: intrinsic_lround_i32_f32:
+; GFX11-GISEL: ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX11-GISEL-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %res = tail call i32 @llvm.lround.i32.f32(float %arg)
+ ret i32 %res
+}
+
+define i32 @intrinsic_lround_i32_f64(double %arg) {
+; GFX9-SDAG-LABEL: intrinsic_lround_i32_f64:
+; GFX9-SDAG: ; %bb.0: ; %entry
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX9-SDAG-NEXT: s_brev_b32 s4, -2
+; GFX9-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x3ff00000
+; GFX9-SDAG-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX9-SDAG-NEXT: v_bfi_b32 v1, s4, v0, v1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX9-SDAG-NEXT: v_cvt_i32_f64_e32 v0, v[0:1]
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: intrinsic_lround_i32_f64:
+; GFX9-GISEL: ; %bb.0: ; %entry
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x3ff00000
+; GFX9-GISEL-NEXT: s_brev_b32 s4, 1
+; GFX9-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, 0, 0
+; GFX9-GISEL-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; GFX9-GISEL-NEXT: v_and_or_b32 v1, v1, s4, v4
+; GFX9-GISEL-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX9-GISEL-NEXT: v_cvt_i32_f64_e32 v0, v[0:1]
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: intrinsic_lround_i32_f64:
+; GFX10-SDAG: ; %bb.0: ; %entry
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX10-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX10-SDAG-NEXT: v_cmp_ge_f64_e64 s4, |v[4:5]|, 0.5
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x3ff00000, s4
+; GFX10-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v0, v1
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SDAG-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX10-SDAG-NEXT: v_cvt_i32_f64_e32 v0, v[0:1]
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: intrinsic_lround_i32_f64:
+; GFX10-GISEL: ; %bb.0: ; %entry
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX10-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, v0, 0, 0
+; GFX10-GISEL-NEXT: v_cmp_ge_f64_e64 s4, |v[4:5]|, 0.5
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x3ff00000, s4
+; GFX10-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v4
+; GFX10-GISEL-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX10-GISEL-NEXT: v_cvt_i32_f64_e32 v0, v[0:1]
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-LABEL: intrinsic_lround_i32_f64:
+; GFX11-SDAG: ; %bb.0: ; %entry
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX11-SDAG-NEXT: v_cmp_ge_f64_e64 s0, |v[4:5]|, 0.5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x3ff00000, s0
+; GFX11-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v0, v1
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX11-SDAG-NEXT: v_cvt_i32_f64_e32 v0, v[0:1]
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: intrinsic_lround_i32_f64:
+; GFX11-GISEL: ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, v0, 0, 0
+; GFX11-GISEL-NEXT: v_cmp_ge_f64_e64 s0, |v[4:5]|, 0.5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x3ff00000, s0
+; GFX11-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX11-GISEL-NEXT: v_cvt_i32_f64_e32 v0, v[0:1]
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %res = tail call i32 @llvm.lround.i32.f64(double %arg)
+ ret i32 %res
+}
+
+define i64 @intrinsic_lround_i64_f32(float %arg) {
+; GFX9-SDAG-LABEL: intrinsic_lround_i64_f32:
+; GFX9-SDAG: ; %bb.0: ; %entry
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX9-SDAG-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
+; GFX9-SDAG-NEXT: s_brev_b32 s4, -2
+; GFX9-SDAG-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX9-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: v_trunc_f32_e32 v0, v0
+; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x2f800000
+; GFX9-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s4
+; GFX9-SDAG-NEXT: v_floor_f32_e32 v1, v1
+; GFX9-SDAG-NEXT: s_mov_b32 s4, 0xcf800000
+; GFX9-SDAG-NEXT: v_fma_f32 v2, v1, s4, |v0|
+; GFX9-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-SDAG-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX9-SDAG-NEXT: v_xor_b32_e32 v0, v2, v3
+; GFX9-SDAG-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX9-SDAG-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v3
+; GFX9-SDAG-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: intrinsic_lround_i64_f32:
+; GFX9-GISEL: ; %bb.0: ; %entry
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX9-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v3, 1
+; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v3, v2
+; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX9-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x2f800000
+; GFX9-GISEL-NEXT: v_mul_f32_e64 v2, |v1|, v2
+; GFX9-GISEL-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xcf800000
+; GFX9-GISEL-NEXT: v_fma_f32 v1, v2, v3, |v1|
+; GFX9-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX9-GISEL-NEXT: v_xor_b32_e32 v0, v1, v3
+; GFX9-GISEL-NEXT: v_xor_b32_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v3
+; GFX9-GISEL-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: intrinsic_lround_i64_f32:
+; GFX10-SDAG: ; %bb.0: ; %entry
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX10-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX10-SDAG-NEXT: v_cmp_ge_f32_e64 s4, |v2|, 0.5
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s4
+; GFX10-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX10-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-SDAG-NEXT: v_trunc_f32_e32 v0, v0
+; GFX10-SDAG-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|
+; GFX10-SDAG-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX10-SDAG-NEXT: v_floor_f32_e32 v1, v1
+; GFX10-SDAG-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v0|
+; GFX10-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX10-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v2
+; GFX10-SDAG-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX10-SDAG-NEXT: v_xor_b32_e32 v0, v0, v3
+; GFX10-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v3
+; GFX10-SDAG-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: intrinsic_lround_i64_f32:
+; GFX10-GISEL: ; %bb.0: ; %entry
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX10-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX10-GISEL-NEXT: v_cmp_ge_f32_e64 s4, |v2|, 0.5
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s4
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v2
+; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX10-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX10-GISEL-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX10-GISEL-NEXT: v_floor_f32_e32 v2, v2
+; GFX10-GISEL-NEXT: v_fma_f32 v1, 0xcf800000, v2, |v1|
+; GFX10-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v1
+; GFX10-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v2
+; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v3
+; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX10-GISEL-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v3
+; GFX10-GISEL-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-LABEL: intrinsic_lround_i64_f32:
+; GFX11-SDAG: ; %bb.0: ; %entry
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX11-SDAG-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
+; GFX11-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX11-SDAG-NEXT: v_trunc_f32_e32 v0, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|
+; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX11-SDAG-NEXT: v_floor_f32_e32 v1, v1
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v0|
+; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX11-SDAG-NEXT: v_xor_b32_e32 v0, v0, v3
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v3
+; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: intrinsic_lround_i64_f32:
+; GFX11-GISEL: ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX11-GISEL-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-GISEL-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_fma_f32 v1, 0xcf800000, v2, |v1|
+; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v1
+; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_xor_b32_e32 v0, v0, v3
+; GFX11-GISEL-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v3
+; GFX11-GISEL-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %res = tail call i64 @llvm.lround.i64.f32(float %arg)
+ ret i64 %res
+}
+
+define i64 @intrinsic_lround_i64_f64(double %arg) {
+; GFX9-SDAG-LABEL: intrinsic_lround_i64_f64:
+; GFX9-SDAG: ; %bb.0: ; %entry
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x3ff00000
+; GFX9-SDAG-NEXT: s_brev_b32 s4, -2
+; GFX9-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; GFX9-SDAG-NEXT: v_bfi_b32 v1, s4, v4, v1
+; GFX9-SDAG-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX9-SDAG-NEXT: s_movk_i32 s4, 0xffe0
+; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX9-SDAG-NEXT: v_ldexp_f64 v[2:3], v[0:1], s4
+; GFX9-SDAG-NEXT: s_mov_b32 s4, 0
+; GFX9-SDAG-NEXT: s_mov_b32 s5, 0xc1f00000
+; GFX9-SDAG-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX9-SDAG-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
+; GFX9-SDAG-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX9-SDAG-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: intrinsic_lround_i64_f64:
+; GFX9-GISEL: ; %bb.0: ; %entry
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x3ff00000
+; GFX9-GISEL-NEXT: s_brev_b32 s4, 1
+; GFX9-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, 0, 0
+; GFX9-GISEL-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; GFX9-GISEL-NEXT: v_and_or_b32 v1, v1, s4, v4
+; GFX9-GISEL-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x3df00000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0xc1f00000
+; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX9-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; GFX9-GISEL-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX9-GISEL-NEXT: v_fma_f64 v[0:1], v[2:3], v[4:5], v[0:1]
+; GFX9-GISEL-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX9-GISEL-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: intrinsic_lround_i64_f64:
+; GFX10-SDAG: ; %bb.0: ; %entry
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX10-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SDAG-NEXT: v_cmp_ge_f64_e64 s4, |v[4:5]|, 0.5
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x3ff00000, s4
+; GFX10-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v4, v1
+; GFX10-SDAG-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX10-SDAG-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX10-SDAG-NEXT: v_ldexp_f64 v[2:3], v[0:1], 0xffffffe0
+; GFX10-SDAG-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX10-SDAG-NEXT: v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
+; GFX10-SDAG-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX10-SDAG-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: intrinsic_lround_i64_f64:
+; GFX10-GISEL: ; %bb.0: ; %entry
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX10-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, v0, 0, 0
+; GFX10-GISEL-NEXT: v_cmp_ge_f64_e64 s4, |v[4:5]|, 0.5
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x3ff00000, s4
+; GFX10-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v4
+; GFX10-GISEL-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX10-GISEL-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX10-GISEL-NEXT: v_mul_f64 v[2:3], 0x3df00000, v[0:1]
+; GFX10-GISEL-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX10-GISEL-NEXT: v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
+; GFX10-GISEL-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX10-GISEL-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-LABEL: intrinsic_lround_i64_f64:
+; GFX11-SDAG: ; %bb.0: ; %entry
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-SDAG-NEXT: v_cmp_ge_f64_e64 s0, |v[4:5]|, 0.5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x3ff00000, s0
+; GFX11-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v4, v1
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX11-SDAG-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_ldexp_f64 v[2:3], v[0:1], 0xffffffe0
+; GFX11-SDAG-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
+; GFX11-SDAG-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX11-SDAG-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: intrinsic_lround_i64_f64:
+; GFX11-GISEL: ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, v0, 0, 0
+; GFX11-GISEL-NEXT: v_cmp_ge_f64_e64 s0, |v[4:5]|, 0.5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x3ff00000, s0
+; GFX11-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX11-GISEL-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_mul_f64 v[2:3], 0x3df00000, v[0:1]
+; GFX11-GISEL-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
+; GFX11-GISEL-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX11-GISEL-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %res = tail call i64 @llvm.lround.i64.f64(double %arg)
+ ret i64 %res
+}
+
+define i64 @intrinsic_llround_i64_f32(float %arg) {
+; GFX9-SDAG-LABEL: intrinsic_llround_i64_f32:
+; GFX9-SDAG: ; %bb.0: ; %entry
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX9-SDAG-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
+; GFX9-SDAG-NEXT: s_brev_b32 s4, -2
+; GFX9-SDAG-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX9-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: v_trunc_f32_e32 v0, v0
+; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x2f800000
+; GFX9-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s4
+; GFX9-SDAG-NEXT: v_floor_f32_e32 v1, v1
+; GFX9-SDAG-NEXT: s_mov_b32 s4, 0xcf800000
+; GFX9-SDAG-NEXT: v_fma_f32 v2, v1, s4, |v0|
+; GFX9-SDAG-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-SDAG-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX9-SDAG-NEXT: v_xor_b32_e32 v0, v2, v3
+; GFX9-SDAG-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX9-SDAG-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v3
+; GFX9-SDAG-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: intrinsic_llround_i64_f32:
+; GFX9-GISEL: ; %bb.0: ; %entry
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX9-GISEL-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
+; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v3, 1
+; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, v3, v2
+; GFX9-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX9-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x2f800000
+; GFX9-GISEL-NEXT: v_mul_f32_e64 v2, |v1|, v2
+; GFX9-GISEL-NEXT: v_floor_f32_e32 v2, v2
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xcf800000
+; GFX9-GISEL-NEXT: v_fma_f32 v1, v2, v3, |v1|
+; GFX9-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX9-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX9-GISEL-NEXT: v_xor_b32_e32 v0, v1, v3
+; GFX9-GISEL-NEXT: v_xor_b32_e32 v1, v2, v3
+; GFX9-GISEL-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v3
+; GFX9-GISEL-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: intrinsic_llround_i64_f32:
+; GFX10-SDAG: ; %bb.0: ; %entry
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX10-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX10-SDAG-NEXT: v_cmp_ge_f32_e64 s4, |v2|, 0.5
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s4
+; GFX10-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX10-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-SDAG-NEXT: v_trunc_f32_e32 v0, v0
+; GFX10-SDAG-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|
+; GFX10-SDAG-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX10-SDAG-NEXT: v_floor_f32_e32 v1, v1
+; GFX10-SDAG-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v0|
+; GFX10-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX10-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v2
+; GFX10-SDAG-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX10-SDAG-NEXT: v_xor_b32_e32 v0, v0, v3
+; GFX10-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v3
+; GFX10-SDAG-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: intrinsic_llround_i64_f32:
+; GFX10-GISEL: ; %bb.0: ; %entry
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX10-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX10-GISEL-NEXT: v_cmp_ge_f32_e64 s4, |v2|, 0.5
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s4
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v2
+; GFX10-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX10-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX10-GISEL-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX10-GISEL-NEXT: v_floor_f32_e32 v2, v2
+; GFX10-GISEL-NEXT: v_fma_f32 v1, 0xcf800000, v2, |v1|
+; GFX10-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v1
+; GFX10-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v2
+; GFX10-GISEL-NEXT: v_xor_b32_e32 v0, v0, v3
+; GFX10-GISEL-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX10-GISEL-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v3
+; GFX10-GISEL-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-LABEL: intrinsic_llround_i64_f32:
+; GFX11-SDAG: ; %bb.0: ; %entry
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX11-SDAG-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
+; GFX11-SDAG-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX11-SDAG-NEXT: v_trunc_f32_e32 v0, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0|
+; GFX11-SDAG-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX11-SDAG-NEXT: v_floor_f32_e32 v1, v1
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v0|
+; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-SDAG-NEXT: v_cvt_u32_f32_e32 v0, v2
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX11-SDAG-NEXT: v_xor_b32_e32 v0, v0, v3
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-SDAG-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v3
+; GFX11-SDAG-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: intrinsic_llround_i64_f32:
+; GFX11-GISEL: ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
+; GFX11-GISEL-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, 0x80000000, v0, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_trunc_f32_e32 v1, v0
+; GFX11-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_mul_f32_e64 v2, 0x2f800000, |v1|
+; GFX11-GISEL-NEXT: v_floor_f32_e32 v2, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_fma_f32 v1, 0xcf800000, v2, |v1|
+; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, v1
+; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v1, v2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_xor_b32_e32 v0, v0, v3
+; GFX11-GISEL-NEXT: v_xor_b32_e32 v1, v1, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v3
+; GFX11-GISEL-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %res = tail call i64 @llvm.llround.i64.f32(float %arg)
+ ret i64 %res
+}
+
+define i64 @intrinsic_llround_i64_f64(double %arg) {
+; GFX9-SDAG-LABEL: intrinsic_llround_i64_f64:
+; GFX9-SDAG: ; %bb.0: ; %entry
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x3ff00000
+; GFX9-SDAG-NEXT: s_brev_b32 s4, -2
+; GFX9-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-SDAG-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; GFX9-SDAG-NEXT: v_bfi_b32 v1, s4, v4, v1
+; GFX9-SDAG-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX9-SDAG-NEXT: s_movk_i32 s4, 0xffe0
+; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX9-SDAG-NEXT: v_ldexp_f64 v[2:3], v[0:1], s4
+; GFX9-SDAG-NEXT: s_mov_b32 s4, 0
+; GFX9-SDAG-NEXT: s_mov_b32 s5, 0xc1f00000
+; GFX9-SDAG-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX9-SDAG-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
+; GFX9-SDAG-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX9-SDAG-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: intrinsic_llround_i64_f64:
+; GFX9-GISEL: ; %bb.0: ; %entry
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x3ff00000
+; GFX9-GISEL-NEXT: s_brev_b32 s4, 1
+; GFX9-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, 0, 0
+; GFX9-GISEL-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v6, vcc
+; GFX9-GISEL-NEXT: v_and_or_b32 v1, v1, s4, v4
+; GFX9-GISEL-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x3df00000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0xc1f00000
+; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX9-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; GFX9-GISEL-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX9-GISEL-NEXT: v_fma_f64 v[0:1], v[2:3], v[4:5], v[0:1]
+; GFX9-GISEL-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX9-GISEL-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: intrinsic_llround_i64_f64:
+; GFX10-SDAG: ; %bb.0: ; %entry
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX10-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-SDAG-NEXT: v_cmp_ge_f64_e64 s4, |v[4:5]|, 0.5
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x3ff00000, s4
+; GFX10-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v4, v1
+; GFX10-SDAG-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX10-SDAG-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX10-SDAG-NEXT: v_ldexp_f64 v[2:3], v[0:1], 0xffffffe0
+; GFX10-SDAG-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX10-SDAG-NEXT: v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
+; GFX10-SDAG-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX10-SDAG-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: intrinsic_llround_i64_f64:
+; GFX10-GISEL: ; %bb.0: ; %entry
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX10-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX10-GISEL-NEXT: v_and_or_b32 v0, v0, 0, 0
+; GFX10-GISEL-NEXT: v_cmp_ge_f64_e64 s4, |v[4:5]|, 0.5
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x3ff00000, s4
+; GFX10-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v4
+; GFX10-GISEL-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX10-GISEL-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX10-GISEL-NEXT: v_mul_f64 v[2:3], 0x3df00000, v[0:1]
+; GFX10-GISEL-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX10-GISEL-NEXT: v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
+; GFX10-GISEL-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX10-GISEL-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-LABEL: intrinsic_llround_i64_f64:
+; GFX11-SDAG: ; %bb.0: ; %entry
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-SDAG-NEXT: v_cmp_ge_f64_e64 s0, |v[4:5]|, 0.5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x3ff00000, s0
+; GFX11-SDAG-NEXT: v_bfi_b32 v1, 0x7fffffff, v4, v1
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX11-SDAG-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_ldexp_f64 v[2:3], v[0:1], 0xffffffe0
+; GFX11-SDAG-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
+; GFX11-SDAG-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX11-SDAG-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: intrinsic_llround_i64_f64:
+; GFX11-GISEL: ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX11-GISEL-NEXT: v_and_or_b32 v0, v0, 0, 0
+; GFX11-GISEL-NEXT: v_cmp_ge_f64_e64 s0, |v[4:5]|, 0.5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 0x3ff00000, s0
+; GFX11-GISEL-NEXT: v_and_or_b32 v1, 0x80000000, v1, v4
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1]
+; GFX11-GISEL-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_mul_f64 v[2:3], 0x3df00000, v[0:1]
+; GFX11-GISEL-NEXT: v_floor_f64_e32 v[2:3], v[2:3]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_fma_f64 v[0:1], 0xc1f00000, v[2:3], v[0:1]
+; GFX11-GISEL-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
+; GFX11-GISEL-NEXT: v_cvt_i32_f64_e32 v1, v[2:3]
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %res = tail call i64 @llvm.llround.i64.f64(double %arg)
+ ret i64 %res
+}
+
+define half @intrinsic_fround_half(half %arg) {
+; GFX9-SDAG-LABEL: intrinsic_fround_half:
+; GFX9-SDAG: ; %bb.0: ; %entry
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_trunc_f16_e32 v1, v0
+; GFX9-SDAG-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x3c00
+; GFX9-SDAG-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff
+; GFX9-SDAG-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX9-SDAG-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: intrinsic_fround_half:
+; GFX9-GISEL: ; %bb.0: ; %entry
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_trunc_f16_e32 v1, v0
+; GFX9-GISEL-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x3c00
+; GFX9-GISEL-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
+; GFX9-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: intrinsic_fround_half:
+; GFX10-SDAG: ; %bb.0: ; %entry
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_trunc_f16_e32 v1, v0
+; GFX10-SDAG-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX10-SDAG-NEXT: v_cmp_ge_f16_e64 s4, |v2|, 0.5
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s4
+; GFX10-SDAG-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX10-SDAG-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: intrinsic_fround_half:
+; GFX10-GISEL: ; %bb.0: ; %entry
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_trunc_f16_e32 v1, v0
+; GFX10-GISEL-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
+; GFX10-GISEL-NEXT: v_cmp_ge_f16_e64 s4, |v2|, 0.5
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s4
+; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-LABEL: intrinsic_fround_half:
+; GFX11-SDAG: ; %bb.0: ; %entry
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_trunc_f16_e32 v1, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX11-SDAG-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
+; GFX11-SDAG-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: intrinsic_fround_half:
+; GFX11-GISEL: ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_trunc_f16_e32 v1, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
+; GFX11-GISEL-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
+; GFX11-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %res = tail call half @llvm.round.f16(half %arg)
+ ret half %res
+}
+
+define i32 @intrinsic_lround_i32_f16(half %arg) {
+; GFX9-SDAG-LABEL: intrinsic_lround_i32_f16:
+; GFX9-SDAG: ; %bb.0: ; %entry
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_trunc_f16_e32 v1, v0
+; GFX9-SDAG-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x3c00
+; GFX9-SDAG-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff
+; GFX9-SDAG-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX9-SDAG-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9-SDAG-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: intrinsic_lround_i32_f16:
+; GFX9-GISEL: ; %bb.0: ; %entry
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_trunc_f16_e32 v1, v0
+; GFX9-GISEL-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x3c00
+; GFX9-GISEL-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
+; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
+; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
+; GFX9-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX9-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX9-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: intrinsic_lround_i32_f16:
+; GFX10-SDAG: ; %bb.0: ; %entry
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_trunc_f16_e32 v1, v0
+; GFX10-SDAG-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX10-SDAG-NEXT: v_cmp_ge_f16_e64 s4, |v2|, 0.5
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s4
+; GFX10-SDAG-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX10-SDAG-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX10-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX10-SDAG-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: intrinsic_lround_i32_f16:
+; GFX10-GISEL: ; %bb.0: ; %entry
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_trunc_f16_e32 v1, v0
+; GFX10-GISEL-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
+; GFX10-GISEL-NEXT: v_cmp_ge_f16_e64 s4, |v2|, 0.5
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s4
+; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX10-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-SDAG-LABEL: intrinsic_lround_i32_f16:
+; GFX11-SDAG: ; %bb.0: ; %entry
+; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-SDAG-NEXT: v_trunc_f16_e32 v1, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX11-SDAG-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
+; GFX11-SDAG-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX11-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-SDAG-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-LABEL: intrinsic_lround_i32_f16:
+; GFX11-GISEL: ; %bb.0: ; %entry
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-NEXT: v_trunc_f16_e32 v1, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
+; GFX11-GISEL-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
+; GFX11-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX11-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %res = tail call i32 @llvm.lround.i32.f16(half %arg)
+ ret i32 %res
+}
+
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