[llvm] 81e2a57 - AMDGPU: Fix assembler asserting on expressions in vop3 instructions (#100103)

[via llvm-commits]

Author: Matt Arsenault
Date: 2024-07-23T18:58:30+04:00
New Revision: 81e2a57b41de9417f7735c53088876d1ef7b555d

URL: https://github.com/llvm/llvm-project/commit/81e2a57b41de9417f7735c53088876d1ef7b555d
DIFF: https://github.com/llvm/llvm-project/commit/81e2a57b41de9417f7735c53088876d1ef7b555d.diff

LOG: AMDGPU: Fix assembler asserting on expressions in vop3 instructions (#100103)

Fixes #100075

---------

Co-authored-by: Jay Foad <jay.foad at amd.com>

Added: 
    llvm/test/MC/AMDGPU/reloc-operands-gfx10.s

Modified: 
    llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 92c3b26ca4d6f..e8ecd26a7d2e5 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -8649,10 +8649,8 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
       Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
     } else if (Op.isImmModifier()) {
       OptionalIdx[Op.getImmTy()] = I;
-    } else if (Op.isRegOrImm()) {
-      Op.addRegOrImmOperands(Inst, 1);
     } else {
-      llvm_unreachable("unhandled operand type");
+      Op.addRegOrImmOperands(Inst, 1);
     }
   }
 

diff  --git a/llvm/test/MC/AMDGPU/reloc-operands-gfx10.s b/llvm/test/MC/AMDGPU/reloc-operands-gfx10.s
new file mode 100644
index 0000000000000..b0fe71ddadb3b
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/reloc-operands-gfx10.s
@@ -0,0 +1,31 @@
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s
+
+; test vop3 operands
+
+// GFX10: v_mad_u32_u24 v0, g0 at abs32@lo, v0, 12   ; encoding: [0x00,0x00,0x43,0xd5,0xff,0x00,0x32,0x02,A,A,A,A]
+// GFX10-NEXT:                                    ;   fixup A - offset: 8, value: g0 at abs32@lo, kind: FK_Data_4
+v_mad_u32_u24 v0, g0 at abs32@lo, v0, 12
+
+// GFX10: v_mad_u32_u24 v0, v0, g0 at abs32@lo, 12   ; encoding: [0x00,0x00,0x43,0xd5,0x00,0xff,0x31,0x02,A,A,A,A]
+// GFX10-NEXT:                                    ;   fixup A - offset: 8, value: g0 at abs32@lo, kind: FK_Data_4
+v_mad_u32_u24 v0, v0, g0 at abs32@lo, 12
+
+// GFX10: v_mad_u32_u24 v0, v0, 12, g0 at abs32@lo   ; encoding: [0x00,0x00,0x43,0xd5,0x00,0x19,0xfd,0x03,A,A,A,A]
+// GFX10-NEXT:                                    ;   fixup A - offset: 8, value: g0 at abs32@lo, kind: FK_Data_4
+v_mad_u32_u24 v0, v0, 12, g0 at abs32@lo
+
+; test vop2 operands
+
+// GFX10: v_add_nc_u32_e32 v0, g0 at abs32@lo, v1    ; encoding: [0xff,0x02,0x00,0x4a,A,A,A,A]
+// GFX10-NEXT:                                    ;   fixup A - offset: 4, value: g0 at abs32@lo, kind: FK_Data_4
+v_add_nc_u32 v0, g0 at abs32@lo, v1
+
+// GFX10: v_add_nc_u32_e64 v0, v1, g0 at abs32@lo    ; encoding: [0x00,0x00,0x25,0xd5,0x01,0xff,0x01,0x00,A,A,A,A]
+// GFX10-NEXT:                                    ;   fixup A - offset: 8, value: g0 at abs32@lo, kind: FK_Data_4
+v_add_nc_u32 v0, v1, g0 at abs32@lo
+
+// test vop1 operands
+// GFX10: v_not_b32_e32 v0, g0 at abs32@lo           ; encoding: [0xff,0x6e,0x00,0x7e,A,A,A,A]
+// GFX10-NEXT:                                    ;   fixup A - offset: 4, value: g0 at abs32@lo, kind: FK_Data_4
+v_not_b32 v0, g0 at abs32@lo
+