[llvm] [RISCV] Add unit strided load/store to whole register peephole (PR #100116)

[Luke Lau via llvm-commits]

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lukel97 wrote:

These functions are marked with optnone so the machine SSA optimisation passes aren't run, including RISCVVectorPeephole.

https://github.com/llvm/llvm-project/pull/100116