[llvm] [AMDGPU] Define constrained multi-dword scalar load instructions. (PR #96161)

[Christudasan Devadasan via llvm-commits]

https://github.com/cdevadas updated https://github.com/llvm/llvm-project/pull/96161

>From a2deed4c08a4bc106af31c6f88ddf9e213295dac Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
Date: Thu, 20 Jun 2024 10:00:59 +0000
Subject: [PATCH 1/3] [AMDGPU] Define constrained multi-dword scalar load
 instructions.

---
 llvm/lib/Target/AMDGPU/SMInstructions.td | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index df1722b1f7fb4..4551a3a615b15 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -167,6 +167,20 @@ multiclass SM_Pseudo_Loads<RegisterClass baseClass,
   def _IMM : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
   def _SGPR : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
   def _SGPR_IMM : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
+
+  // The constrained multi-dword load equivalents with early clobber flag at
+  // the dst operand. They are needed only for codegen and there is no need for
+  // their real opcodes.
+  let SubtargetPredicate = isGFX8Plus,
+      Constraints = !if(!gt(dstClass.RegTypes[0].Size, 32),
+                         "@earlyclobber $sdst", "") in {
+    let PseudoInstr = NAME # !cast<OffsetMode>(IMM_Offset).Variant in
+      def _IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
+    let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_Offset).Variant in
+      def _SGPR_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
+    let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_IMM_Offset).Variant in
+      def _SGPR_IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
+  }
 }
 
 multiclass SM_Pseudo_Stores<RegisterClass baseClass,

>From f64ad28a28ce2c8db17aa3e74ec026ca9089baf5 Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
Date: Thu, 20 Jun 2024 14:41:06 +0000
Subject: [PATCH 2/3] skip _ec ld insn when data size is lesser or equal to 32.

---
 llvm/lib/Target/AMDGPU/SMInstructions.td | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 4551a3a615b15..137acd3130731 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -171,15 +171,15 @@ multiclass SM_Pseudo_Loads<RegisterClass baseClass,
   // The constrained multi-dword load equivalents with early clobber flag at
   // the dst operand. They are needed only for codegen and there is no need for
   // their real opcodes.
-  let SubtargetPredicate = isGFX8Plus,
-      Constraints = !if(!gt(dstClass.RegTypes[0].Size, 32),
-                         "@earlyclobber $sdst", "") in {
-    let PseudoInstr = NAME # !cast<OffsetMode>(IMM_Offset).Variant in
-      def _IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
-    let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_Offset).Variant in
-      def _SGPR_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
-    let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_IMM_Offset).Variant in
-      def _SGPR_IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
+  if !gt(dstClass.RegTypes[0].Size, 32) then {
+    let SubtargetPredicate = isGFX8Plus, Constraints = "@earlyclobber $sdst" in {
+      let PseudoInstr = NAME # !cast<OffsetMode>(IMM_Offset).Variant in
+        def _IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
+      let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_Offset).Variant in
+        def _SGPR_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
+      let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_IMM_Offset).Variant in
+        def _SGPR_IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
+    }
   }
 }
 

>From 2850b4ff0695f9db07647f3b8f580da3df965751 Mon Sep 17 00:00:00 2001
From: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
Date: Wed, 3 Jul 2024 03:26:29 +0000
Subject: [PATCH 3/3] handle the pseudo instruction defs inside a multiclass.

---
 llvm/lib/Target/AMDGPU/SMInstructions.td | 35 ++++++++++++------------
 1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 137acd3130731..de8f0f9cd62c3 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -161,26 +161,25 @@ class SM_Discard_Pseudo <string opName, OffsetMode offsets>
   let has_soffset = offsets.HasSOffset;
 }
 
-multiclass SM_Pseudo_Loads<RegisterClass baseClass,
-                           RegisterClass dstClass> {
-  defvar opName = !tolower(NAME);
-  def _IMM : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
-  def _SGPR : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
-  def _SGPR_IMM : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
+multiclass SM_Load_Pseudos<string op, RegisterClass baseClass,
+                           RegisterClass dstClass, OffsetMode offsets> {
+  defvar opName = !tolower(op);
+  def "" : SM_Load_Pseudo <opName, baseClass, dstClass, offsets>;
 
   // The constrained multi-dword load equivalents with early clobber flag at
-  // the dst operand. They are needed only for codegen and there is no need for
-  // their real opcodes.
-  if !gt(dstClass.RegTypes[0].Size, 32) then {
-    let SubtargetPredicate = isGFX8Plus, Constraints = "@earlyclobber $sdst" in {
-      let PseudoInstr = NAME # !cast<OffsetMode>(IMM_Offset).Variant in
-        def _IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
-      let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_Offset).Variant in
-        def _SGPR_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
-      let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_IMM_Offset).Variant in
-        def _SGPR_IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
-    }
-  }
+  // the dst operands. They are needed only for codegen and there is no need
+  // for their real opcodes.
+  if !gt(dstClass.RegTypes[0].Size, 32) then
+    let Constraints = "@earlyclobber $sdst",
+        PseudoInstr = op # offsets.Variant in
+      def "" # _ec : SM_Load_Pseudo <opName, baseClass, dstClass, offsets>;
+}
+
+multiclass SM_Pseudo_Loads<RegisterClass baseClass,
+                           RegisterClass dstClass> {
+  defm _IMM : SM_Load_Pseudos <NAME, baseClass, dstClass, IMM_Offset>;
+  defm _SGPR : SM_Load_Pseudos <NAME, baseClass, dstClass, SGPR_Offset>;
+  defm _SGPR_IMM : SM_Load_Pseudos <NAME, baseClass, dstClass, SGPR_IMM_Offset>;
 }
 
 multiclass SM_Pseudo_Stores<RegisterClass baseClass,