[llvm] 8a615bc - [LoongArch] Summary the release notes for LLVM 19

[Weining Lu via llvm-commits]

Author: Weining Lu
Date: 2024-07-23T15:19:07+08:00
New Revision: 8a615bcf2f8c8140c6eadae964c8ea7fb4cfee33

URL: https://github.com/llvm/llvm-project/commit/8a615bcf2f8c8140c6eadae964c8ea7fb4cfee33
DIFF: https://github.com/llvm/llvm-project/commit/8a615bcf2f8c8140c6eadae964c8ea7fb4cfee33.diff

LOG: [LoongArch] Summary the release notes for LLVM 19

Added: 
    

Modified: 
    clang/docs/ReleaseNotes.rst
    llvm/docs/ReleaseNotes.rst

Removed: 
    


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diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index a72e8c60b14c4..3705d698b4e92 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -1228,6 +1228,14 @@ Windows Support
 LoongArch Support
 ^^^^^^^^^^^^^^^^^
 
+- ``-march=la64v1.0`` and ``-march=la64v1.1`` have been added to select the
+  ``la64v1.0`` and ``la64v1.1`` architecture respectively. And ``-march=la664``
+  is added to support the ``la664`` micro-architecture.
+- The 128-bits SIMD extension (``LSX``) is enabled by default.
+- ``-msimd=`` has beend added to select the SIMD extension(s) to be enabled.
+- Predefined macros ``__loongarch_simd_width`` and ``__loongarch_frecipe`` are
+  added.
+
 RISC-V Support
 ^^^^^^^^^^^^^^
 

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index ce4f0343aea27..a81caa160883d 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -166,6 +166,13 @@ Changes to the LoongArch Backend
 * i32 is now a native type in the datalayout string. This enables
   LoopStrengthReduce for loops with i32 induction variables, among other
   optimizations.
+* Codegen support is added for TLS Desciptor.
+* Interleaved vectorization and vector shuffle are supported on LoongArch and
+  the experimental feature ``auto-vec`` is removed.
+* Allow ``f16`` codegen with expansion to libcalls.
+* Clarify that emulated TLS is not supported.
+* A codegen issue for ``bstrins.w`` is fixed on loongarch32.
+* Assorted codegen improvements.
 
 Changes to the MIPS Backend
 ---------------------------