[llvm] [GISel][TableGen] Generate getRegBankFromRegClass (PR #99896)

[Pierre van Houtryve via llvm-commits]

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@@ -287,8 +291,88 @@ void RegisterBankEmitter::emitBaseClassImplementation(
      << "  for (auto RB : enumerate(RegBanks))\n"
      << "    assert(RB.index() == RB.value()->getID() && \"Index != ID\");\n"
      << "#endif // NDEBUG\n"
-     << "}\n"
-     << "} // end namespace llvm\n";
+     << "}\n";
+
+  uint32_t NoRegBanks = Banks.size();
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Pierre-vh wrote:

very very tiny nit, but at first I thought this meant "no reg bank" as if it's a negative.
Maybe use `N` or `Num`?

https://github.com/llvm/llvm-project/pull/99896