[llvm] [DAG] Reducing instructions by better legalization handling of AVGFLOORU for i128 data types (PR #99913)

[Simon Pilgrim via llvm-commits]

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@@ -9352,6 +9353,27 @@ SDValue TargetLowering::expandAVG(SDNode *N, SelectionDAG &DAG) const {
     }
   }
 
+  if (Opc == ISD::AVGFLOORU && SVT == MVT::i128) {
+    SDValue UAddWithOverflow = DAG.getNode(ISD::UADDO, dl, 
+                                           DAG.getVTList(VT, MVT::i1), { RHS, LHS });
+
+    SDValue Sum = UAddWithOverflow.getValue(0);
+    SDValue Overflow = UAddWithOverflow.getValue(1);
+
+    // Right shift the sum by 1
+    SDValue One = DAG.getConstant(1, dl, VT);
+    SDValue LShrVal = DAG.getNode(ISD::SRL, dl, VT, Sum, One);
+    
+    // Creating the select instruction
+    APInt SignMin = APInt::getSignedMinValue(VT.getSizeInBits());
+    SDValue SignMinVal = DAG.getConstant(SignMin, dl, VT);
+    SDValue ZeroOut = DAG.getConstant(0, dl, VT);
+
+    SDValue SelectVal = DAG.getSelect(dl, VT, Overflow, SignMinVal, ZeroOut);
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RKSimon wrote:

We might be better off zero-extending the overflow bit to SVT and shifting to the MSB (VT.getScalarSizeInBits() - 1)?

https://github.com/llvm/llvm-project/pull/99913